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Lab 9 D-Flip Flops: Shift Register and Sequence Counter
- 1. Katrina Little Experiment #9 Designing with D-Flip Flops: Shift Register and Sequence Counter
- 2. Objective: Introduce the design of sequential circuits using D- Flip Flops. Implement a 4-bit parallel, right shift, load register. Design and build a sequence counter using D- Flip Flop Equipment List: BASYS1 (Spartan 3e family) board Xilinx ISE foundation Generated bit file Part I: Shift Register Block Diagram: Figure I.a Block diagram of a parallel in parallel out shift register. For the experiment, the outputs will be called O3, O2, O1, O0 respectively.
- 3. Background: Given 4 D flip-flops with inputs D0, D1, D2, D3, and outputs O0, O1, O2, O3, a right shift produces an output of D0 O0, O0 O1, O1 O2, and O2 O3. In this case, the original content of Q3 is lost. A shift left operation produces an output O0 O1, O1 O2, O2 Q3, and O3 D3. In the shift left case, the original content of 00 is lost. A shift register can also have a parallel load feature that allows all of the D flip-flops to be loaded in one clock edge to produce D0 O0, D1 O1, D2 O2, and D3 O3. Design Methodology: Inputs Next State Action sh(shift) ld(load) O3 O2 O1 O0 0 0 O3 O2 O1 O0 no change (hold) 0 1 D3 D2 D1 D0 load 1 X SI Q3 Q2 Q1 right shift Table I.a Logic behind a right shift register. When sh =ld =0 no state change occurs (the register is in a hold state.) When sh = 0 ld =1 the register loads the inputs with data. when sh = 1. ld =X the register right shifts. NOTE: Next state action only occurs at rising edges of the clock!! The same logic was applied to left shift. Figure I.b Sample timing diagram for a right shift register with that operates on the falling edge of the clock. As you can see, when load = shift = 0, the outputs hold. When shift =0 and load = 1, the outputs get loaded with the inputs. (Q3 = D3, Q2= D2, Q1 =D1, Q0 =D0) Finally when shift =1 and load =X, you can see that right shift occurs, (Q3 gets the serial input, Q2 gets the current value of Q1, Q1 gets the value of Q2 and Q0 gets the value of Q1)
- 4. Design Specification Plan: ‘ Figure I.c Configuration of 7495 shift register. The clock will NOT be run on an inverter since we want it to operate on the rising edges. The load, clock, and shift of each flip flop will be connected to a 4-bit bus. The design will be similar to this for the experiment. Figure I.d Debouncer that will be added to the shift register to prevent outputs from “jumping”.
- 5. Test Plan (Procedure): 1. Design the four bit left and right shift register in the schematic tool of the ISE using four D flip-flops (Symbols – Categories (Flip Flop) – Symbols (fd)) one for each bit of storage. Draw a logic schematic in your notebook of the final design. The clock input should be connected to a push button so that every time the push button is pressed, the shift register sees a clock pulse to either load data into it or shift its data left or right. Switches are notorious of producing many edge transitions when they go from ‘on’ to ‘off’ or ‘off’ to ‘on.’ These extra edges result in extra clock edges to the shift register clock input when a single clock edge is expected. Since the D flip-flops are edge triggered in the shift register, these extra edges result in the shifting of its bits by more than one bit at a time. 2. Consider the switch de-bounce circuit given below. The CLK input should be connected to push button 0 (BTN0) and the CLK25MHz should be connected to pin 54 of the FPGA, which is a 25 MHz clock input. The circuit works as follows: When CLK input is ‘0’, the 4 and 16 bit counters are cleared and held at a count of zero. Also the terminal count TC output on the 4 bit counter is zero during a clear operation. When CLK input is ‘1’, the clear line is set to zero and the count enable CE inputs to the counters are set to one allowing the counters to start counting up. When the count of 220 -1 (20 bits = 16 bits + 4 bits) is reached, the terminal count TC output is set to ‘1’ on the four bit counter. It takes a total time of (220 -1) /25,000,000 = 0.04794 seconds for the TC output to go high. By this time the switch contact noise has diminished. When the TC on the four bit counter goes high, it sets one of the inputs to the AND gate to zero and thus prevents the counter from counting any further until the CLK input goes low. Hence, this produces a single rising edge on the TC output from the four bit counter independent of the number of edges on the input clock CLK. If the CLK line is noisy producing many edges then the counter is reset and is delayed until the TC on the four bit counter is set to one. In summary, this circuit solves the problem of many
- 6. edges on the CLK input due to switch contact noise (switch bounce) and the output from this circuit produces a clean rising edge on the TC output of the four bit counter. This rising edge can be used to clock the shift register without any switch noise. 3. Simulate the circuit designed in Step 1 and verify that it correctly implements the function of a left / right shift register. Ignore the de-bounce circuit discussed in step 2 above for this simulation. 4. Download this circuit implemented in Step 3 to the BASYS board with D0 through D3 set to SW0 – SW3 and O0 through O3 set to LED0 – LED3. The LOAD input should be connected to SW7, L/R should be on SW6, and the CLK input should be connected to push button 0 (BTN0). You will need to overwrite the pin for the CLK signal. Please ignore the warning in the PACER program due to over riding the global clock pin to push button 0. Ignore the de-bounce circuit for this step. Refer to Table I.b below: Inputs Switch Pin# Outputs LED Pin# D(0) SW0 38 O(0) LED0 15 D(1) SW1 36 O(1) LED1 14 D(2) SW2 29 O(2) LED2 8 D(3) SW3 24 O(3) LED3 7 Table I.b 5. Use the EXPORT program to download the program. Run several cases showing that the shift register works correctly. Describe what is observed during these tests in your laboratory report. 6. Modify the shift register circuit of steps 1, 3, 4, and 5 above to include the de-bounce circuit of step 2. Connect the push button 0 to the CLK input which is one of the inputs of the AND gate shown in figure above. The output of this AND gate is connected to the count enable CE input of the 16 bit counter. Make sure that the 25MHz Clock input is connected to pin P54, which forms the clock inputs for the 4 and 16 bit counters. Finally, tie the terminal count TC output of the four bit counter to the clock inputs of the four D flip-flops of the shift register. Refer to table I.c below: Inputs/Outputs Push Button Pin# clock BTN0 69 clock (25MHz) 54 Table I.c
- 7. 7. Download the design in Step 6 to the BASYS board with D0 through D3 set to SW0 – SW3 and O0 through O3 set to LED0 - LED3. The LOAD input should be connected to SW7, L/R should be on SW6, and the CLK input should be connected as described in step 6. This signal will need its pin over written. Ignore the warning in the PACER program due to overriding the global clock pin to push button 0. This step includes the de-bounce circuit given in step 2. Refer to table I.d below: Input Switch Pin# load SW7 6 L/R shift SW6 10 Table I.d 8. Use the EXPORT program to download the program. Run several cases showing that the shift register works correctly. Describe what is observed during these tests in your laboratory report. Compare the results obtained in this step to that of step 5. Include this comparison in your laboratory report for this experiment.
- 8. Part II: Sequence Counter Block Diagram: Design Methodology: 0000 0010 0100 01100001 0011 0101 0111 DCBA D+C+B+A+ 0000 0010 0001 0011 0010 0100 0011 0101 0100 0110 0101 0111 0110 0001 0111 0000 1000 XXXX 1001 XXXX 1010 XXXX 1011 XXXX 1100 XXXX 1101 XXXX 1110 XXXX 1111 XXXX A+ B+ 0 0 X X 1 1 X X 1 1 X X 1 1 X X 1 0 X X 0 0 X X 0 1 X X 0 0 X X C+ D+ 0 1 X X 0 0 X X 0 1 X X 0 0 X X 1 0 X X 0 0 X X 1 0 X X 0 0 X X Figure II.a Sequence counts: 0,2,4,6,1,3,5,7…repeat
- 9. The following equations can be written from the K-maps: D+ = A’ C+ = A’B’C +BC’ B+ = C’ A+ = C’D + A’B’ + BC’D’ Test Plan (Procedure): 1. Design the sequence counter in the schematic tool of the ISE using the require number of D flip-flops (fd) under Flip Flop category (one for each bit of storage). Draw a logic schematic in your notebook of the final design. 2. Simulate the design implemented in Step 1 and verify that is correctly implements the sequence counter. Ignore the de-bounce circuit in step 2 above when performing the simulation. 3. Download the design in Step 1 to the BASYS board with O0 through ON set to LED0 to LEDN (N is the number of bits required to implement the sequence counter). The CLK input should be connected to push button 0. Use the EXPORT program to download this circuit to the FPGA. Generate a new state transition table to verify that the design works correctly. Ignore the de-bounce circuit in step 2. Describe what was observed during this test in you laboratory report. Refer to table II.a. Input/Output LED Push button Pin# O0 LED0 15 O1 LED1 14 O2 LED2 8 O3 LED3 7 CLK 0 69 Table II.a
- 10. 4. Modify the sequence counter circuit of steps 1, 2, and 3 above to include the de-bounce circuit of step 2 of Part 1 of this experiment. Connect the push button 0 to the CLK input which is one of the inputs of the AND gate shown in figure above. The output of this AND gate is connected to the count enable CE input of the 16 bit counter. Make sure that the 25MHz Clock input is connected to pin P54, which forms the clock inputs for the 4 and 16 bit counters. Finally, tie the terminal count TC output of the four bit counter to the clock inputs of the four D flip-flops of the sequence counter. Input Push Button Pin# CLK 0 69 CLK (25MHz) 54 5. Download the design in Step 4 to the BASYS board with O0 through ON set to LED0 to LEDN. The CLK input should be connected to push button 0. Use the EXPORT program to download the program. Generate a new state transition table to verify that the design works correctly. Include the de-bounce circuit in step 2 of Part 1. Describe what is observed during these tests in your laboratory report. Compare the results obtained in this step to that of step 3. Include this comparison in the laboratory report. Conclusion: For both parts I&II, if noise was present the outputs would “jump” when the clock was activated. If Do was connected to O3 during left-shift O3 would return Do. Similarly, if D3 was connected to O0 during a right-shift O0 would return D3. A don’t care in the next states would make the transition of state impossible to predict if the “in” and “out” of a state were both don’t cares. This situation could be avoided by making a chain of command of each in/ out
- 11. transition. D- flip flops are edge triggered. Therefore, if using switches it makes it difficult to clock the outputs correctly. The clock would also be changing continuously which would change the outputs unless the switch were at zero. An 8 bit register could be constructed as follows: The objectives of the lab were completed successfully. Knowledge of registers and sequence counters have been expanded and designs of both were implemented as planned.