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Article

A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor

1
Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
2
University of Chinese Academy of Sciences, Beijing 100049, China
3
Beijing Key Laboratory for Next Generation RF Communication Chip Technology, Beijing 100029, China
*
Authors to whom correspondence should be addressed.
Electronics 2024, 13(2), 366; https://doi.org/10.3390/electronics13020366
Submission received: 21 December 2023 / Revised: 11 January 2024 / Accepted: 11 January 2024 / Published: 15 January 2024
(This article belongs to the Section Circuit and Signal Processing)

Abstract

:
Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals with low-level amplitudes (from tens of μV to tens of mV) and broadband low-frequency ranges (from sub-Hz to several hundred Hz). Possessing a high input impedance, an instrumentation amplifier (IA) accurately amplifies signals with low amplitude and low frequency, making it suitable for AFE circuits. This work demonstrates a capacitively coupled IA whose feedback resistance is realized by the proposed hybrid resistor, consisting of a switched-capacitor low-pass filter, a switched-capacitor resistor, and a continuous-time low-pass filter. The capacitively coupled IA achieves tera-ohm (TΩ) resistance and is insensitive to process, voltage, and temperature (PVT) variations. The simulation results show that the proposed IA illustrates a high-pass corner of 73.9 mHz, and the change of its high-pass corner with temperature is 0.05 mHz/°C. With the variation in the PVT corners, the difference between the maximum and minimum values of the high-pass corner of the proposed capacitively coupled IA is only 0.06 Hz. The design was implemented in a 130 nm standard CMOS process. The AFE with the proposed capacitively coupled IA achieves a 53.9 dB signal-to-noise and distortion ratio (SNDR) and 69.5 dB total harmonic distortion (THD).

1. Introduction

With the booming of the biomedical industry, wearable biomedical devices have recently attracted wide attention [1,2,3]. Physiological signal acquisition chips based on the CMOS process are one of the important building blocks of wearable devices [1,4], whose design must meet a series of specification requirements for both analog and digital circuits. Analog front-end (AFE) circuits play an important role in the acquisition of physiological signals and must be designed compatible with the properties of physiological signals [5] that have low-level amplitudes (from tens of μV to tens of mV) and appear mostly in different low-frequency ranges (from sub-Hz to several hundred Hz) [6]. In addition, unprocessed DC offset voltages at the interface hinder the accurate acquisition of physiological signals [7]. Therefore, the AFE needs amplification, analog-to-digital conversion, and high-pass filtering to satisfy the physiological signal acquisition [8]. As the high-pass corner is generally lower than 1 Hz [9], the instrumentation amplifier (IA) has a high input impedance and accurately amplifies signals with low amplitude and low frequency, making it a good choice for AFE circuits [10].
Capacitively coupled structures are one of the most popular topologies used in IAs for physiological signal processing [6,11]. They ensure that the amplifier has a large DC input impedance and better suppression of the electrode DC offset (EDO). Moreover, when the input capacitance is less than 100 pF, the signal attenuation at the electrode is ignored [12]. The transfer characteristic of a capacitively coupled IA demonstrates band-pass features with a typical topology that is shown in Figure 1. Achieving a low high-pass corner requires an on-chip resistor of a giga-ohm (GΩ) or more, which is typically implemented via three methods, i.e., duty-cycled resistors (DCRs) [12], pseudo-resistors (PRs) [13], and switched-capacitor resistors (SCRs) [14].
Chandrakumar et al. [15] described the DCR methods. The resistance is adjusted by controlling the duty cycle of the clock. A passive resistor R is placed in series with a switch, which is closed for a short duration every period. D is the duty cycle of the clock driving the switch. Therefore, DCRs magnify the resistance value to R/D. However, owing to variations in the process, voltage, and temperature (PVT), the duty cycle of a DCR cannot be implemented accurately, leading to considerable variations in the resistances [8]. Another problem of the DCR is parasitic capacitance. Paper [12] achieved a significant equivalent resistance value with the DCR method. However, due to the parasitic capacitance, the maximum achievable resistance value was limited. Paper [16] proposed an effective solution to the parasitic capacitance using a multi-rate duty-cycled resistor, which increased the maximum resistance of DCR by 32 times. Nevertheless, the PVT variation in DCRs was not yet discussed in [16].
PRs have a simple structure, allowing for trade-offs between power and area-on-chip [17]. Many capacitively coupled IAs with feedback resistors use PRs to achieve high resistance values for the realization of high-pass corners below 1 Hz [7,9,18]. However, PRs’ linearity (the dependency of the resistance to applied voltage) and impedance are limited by the nonlinear MOS transistors in weak inversion [19]. PRs’ values vary greatly as the applied voltage changes. Therefore, IA, which only uses a PR as a feedback resistance, only processes physiological signals at the μV level and cannot tolerate a large voltage swing across the terminals [20,21,22]. As the amplitude of the physiological signals increases up to the mV level [23,24,25], the resistance value of the conventional PR shows nonlinear fluctuations. Thus, the IA, with only the PR as the feedback resistor, has non-linearity problems in transmitting signals, which makes it challenging to realize the purpose of the high-pass corner below 1 Hz. Moreover, PRs are sensitive to PVT variations, and the value varies by a factor of 100 [12]. Paper [8] proposed a PR calibration circuit that is appropriately adjusted to make the circuit more robust under different processes and temperatures. However, it performs better only at specific corners and temperatures. Paper [18] proposed a novel tunable PR to achieve hundreds of GΩ-level resistances and concurrently reduced the effect of PVT on PR. Nevertheless, its measured high-pass corner is larger than 1 Hz, which cannot realize the requirement of physiological signals with lower frequency.
SCRs are a balanced choice for obtaining a high equivalent resistance value and maintaining PV-robust properties [18]. Moreover, the linearity of an SCR is better and the equivalent resistance value is realized exactly with a certain frequency and capacitance. However, the capacitively coupled IA, with only an SCR as the feedback resistor, will be limited by the frequency of the physiological signal, making the equivalent resistance value of the SCR highly restricted. Paper [14] modified the switched-capacitor structure and proposed a series-to-parallel charge-sharing technique, indicating that the equivalent resistance is ten times that of a conventional SCR. Paper [26] uses a switched-capacitor ladder to achieve an on-chip linearly tunable tera-ohm (TΩ) resistor, and the linear tuning of the resistance is realized by controlling the sampling frequency. However, because of the sampling action of the switches in the SCR, unexpected and unavoidable spike signals are generated at multiples of the clock frequencies. Therefore, a filtering operation of these spike signals is required.
To summarize, three main methods are used for generating large equivalent resistance and low-frequency high-pass corners. DCRs amplify the equivalent resistance value by a multiple of the reciprocal of the duty cycle. Although they have simple structures, they are sensitive to PVT variations and parasitic capacitors. PRs have area efficiency; however, they are limited by the non-linearity problem and is also sensitive to PVT variations. SCRs achieve high equivalent resistance values and maintain PVT robustness. Nevertheless, spike signals exist. Thus, this paper proposes a topology with a combination of an SCR and a PR structure, which is called the switched-capacitor filter–switched-capacitor resistor–pseudo-resistor (SSP) hybrid feedback resistor, including a high SCR and two low-pass filters. The proposed SSP feedback resistor has the advantages of both SCRs and PRs. The proposed topology forms the equivalent feedback resistance of the capacitively coupled IA, allowing it to realize higher resistance values. Hence, a high-pass corner below 1 Hz is achieved while ensuring the PVT robustness of the IA.
This paper is organized as follows. Section 2 theoretically analyzes the proposed IA with PVT robustness and a sub-Hz high-pass corner and discusses the detailed circuit implementation of IA. Section 3 presents the simulated results of the proposed IA, followed by the conclusion in Section 4.

2. Design and Analysis of the Proposed Structure

2.1. Theoretical Analysis of the Capacitively Coupled IA

A top-level schematic of the traditional capacitively coupled IA is shown in Figure 2. The capacitively coupled IA adopted a fully differential form, consisting mainly of a fully differential amplifier (AMP), an input coupling capacitor C I N , a feedback capacitor C F B , and an equivalent feedback resistor R F B . The traditional capacitively coupled IA with band-pass characteristics has a gain A V and a high-pass corner frequency f H P , respectively, as follows:
A V = C I N C F B ,
f H P = 1 2 π R F B C F B ,
Since the physiological signals have a low frequency, considerable DC interference is introduced at its interface when the physiological signals are measured. Thus, the capacitively coupled IA applied to physiological signals requires a high-pass filtering operation with a high-pass corner of less than 1 Hz to suppress the DC component to prevent saturation; this also ensures that the measured input signal can be amplified appropriately.
Equation (1) shows that C I N and C F B require a significant ratio relationship to ensure that the capacitively coupled IA has an appropriate gain. Due to the value of the on-chip capacitance being relatively low, a high value of the feedback capacitance C F B cannot be achieved due to area efficiency considerations. Equation (2) shows that the feedback capacitance C F B and the feedback resistance R F B determine the high-pass corner frequency f H P of the capacitively coupled IA. Therefore, an f H P below 1 Hz sets a stringent requirement on the value of R F B . If we assume that C F B = 400 fF, it requires a value of R F B higher than 400 GΩ to realize f H P < 1 Hz. Moreover, when designing a capacitively coupled IA in practice, the f H P of the capacitively coupled IA is usually expected to be much lower, rather than around 1 Hz. This means that it is desirable to realize the equivalent resistance value of R F B at the TΩ level. Using PRs to achieve such a high equivalent resistance of R F B is an area-efficient method. However, PRs have poor linearity and are sensitive to PVT variations. An alternative method that has PVT robustness and can realize large resistances is the SCR. However, the maximum equivalent resistance value that an SCR can achieve is limited. The equivalent resistance R C value of an SCR is:
R C = 1 f C C C ,
where f C is the switching frequency, and C C is the capacitance value of the switched capacitor. In [27], it was shown that the switching frequency should be at least twice the signal bandwidth to satisfy the Nyquist–Shannon sampling theorem to prevent signal aliasing. This means it requires f C 2 f S I G N A L ( f S I G N A L is the frequency of the signal being processed). The bandwidth of a physiological signal amplifier is usually a few thousand Hz or a few hundred Hz, and the value of the on-chip capacitance typically ranges from fF to pF. According to Equation (3), assuming an ideal situation with f C = 1 kHz and C C = 10 fF, the value of R C that can be obtained is 100 GΩ. Therefore, if an SCR is directly used as the feedback resistor R F B of the capacitively coupled IA, the resistance value of R F B will be significantly limited. Thus, the goal of a high-pass corner of a capacitively coupled IA of less than 1 Hz cannot be realized. In addition, the switched sampling of the switch capacitor structure can cause undesired spike signals at multiples of the clock frequencies.
This paper proposes an SSP hybrid feedback resistor. The proposed hybrid feedback resistor realizes TΩ-level equivalent resistance. Moreover, it filters out the spike signals caused by the sampling action in the switched-capacitor structure.

2.2. Circuit Implementation

2.2.1. SSP Hybrid Feedback Resistor

The SSP hybrid feedback resistor proposed in this paper is shown in Figure 3. The SSP hybrid feedback resistor consists of three parts: the switched-capacitor filter LPF1, the equivalent resistance R S C of the SCR, and the continuous-time filter LPF2. It can be seen that the feedback output signal V O U T first passes through the low-pass filter LPF1, which consists of a switched-capacitor structure, after which it passes through an equivalent resistance R S C of the SCR and finally is fed back to the input terminal after it passes through the continuous-time low-pass filter LPF2. LPF1, in the first part, allows for low-pass pre-filtering of the feedback signal from the output to the input. Moreover, LPF1 enables the value of the switching frequency in the SCR of the second part to be unrestricted by the frequency of the processed signal. The SCR in the second part is used to generate an extremely high resistance value. LPF2, in the third part, performs a further low-pass filtering of the feedback signal. In addition, the spike signals generated in the first and second parts due to the sampling action of the switches can be filtered out by LPF2.
The low-pass filter LPF1 demonstrated in Figure 3a acts as an isolation between the output signal V O U T and the equivalent resistance R S C of the SCR. According to the Nyquist–Shannon sampling theorem, the switching frequency f A controlling the switched-capacitor low-pass filter LPF1 must be greater than twice the output signal frequency f S I G N A L . This allows the switching frequency f B , which controls the equivalent resistance R S C of the SCR, as illustrated in Figure 3b, to be independent of 2 f S I G N A L . Therefore, the range of values for the switching frequency f B can be reduced to a lower value, resulting in a higher value of the equivalent resistance R S C of the SCR. In addition, the low-pass filter LPF1 can filter the signal feedback from the output to the input, making the feedback common-mode signal unaffected by the higher-frequency output signal. Due to the sampling action of the switched-capacitor low-pass filter LPF1 and the equivalent resistor R S C of the SCR, unexpected spike signals are generated at multiples of the clock frequencies. Therefore, a continuous-time low-pass filter LPF2 is used after the low-pass filter LPF1 and the equivalent resistance R S C of the SCR is used to filter out unexpected spike signals. The continuous-time low-pass filter LPF2 is formed by the equivalent resistance R P of the PR and capacitor C 4 , as shown in Figure 3c.
PRs can achieve high impedance in integrated circuits without occupying a large area and are used in many integrated circuits that require high time constants without precise resistance values [28]. In this design, the low-pass filter LPF2 with a PR requires a low cutoff frequency, so it only needs the resistance value of the equivalent resistor R P of the PR to be greater than a particular value in the expected signal range to achieve continuous filtering. The PR in LPF2 is shown in Figure 4a. The equivalent resistance R P of the PR is designed by layout in the CMOS process, and its resistance characteristics are simulated by adding different voltages at its two terminals, as shown in Figure 4b. The simulation shows that the resistance value of R P is always greater than 500 GΩ when the voltage variation at both terminals of R P is less than 300 mV. The value of the on-chip capacitance typically ranges from fF to pF. According to f L P F 2 = 1 2 π R P C 4 , the cutoff frequency f L P F 2 of the continuous-time low-pass filter can be designed to be very low, which enables filtering out of the spike frequency generated by the switches and thus achieves continuous filtering.

2.2.2. Push–Pull Amplifier

The schematic diagram of the AMP used in the capacitively coupled IA is shown in Figure 5. The AMP is formed by a fully differential push–pull structure, which allows the AMP to obtain a more efficient gain factor. The main AMP section implements a signal amplification function, while the common mode feedback (CMFB) section ensures the stability of the common mode output voltage. This makes the overall circuit operate correctly.

2.2.3. The Proposed IA

The top-level schematic and the timing diagram of the proposed capacitively coupled IA are shown in Figure 6a and Figure 6b, respectively. The SSP hybrid feedback resistor is implemented in the feedback loop of the proposed capacitively coupled IA. This allows the capacitively coupled IA to achieve a high-pass corner below 1 Hz while maintaining PVT robustness. Moreover, the acquired physiological signals are accurately amplified to allow the signal to be processed by the back-stage circuits. f A ( f A ) and f B ( f B ) are the switching frequencies of the corresponding switches in the SSP hybrid feedback resistor, and the four switches operate alternately to realize the timing required for the capacitively coupled IA.
Note that the switching frequencies are f A = 100 Hz and f B = 1 Hz, as shown in Figure 6b. However, f A and f B are not fixed values. Figure 6b is only used as an example to show their duty cycle and proportionality. While satisfying the design specifications, f A and f B are adjustable according to the actual requirements of the circuit. In addition, the PR has a very large nonlinearity. However, a continuous-time type resistor with a very high resistance value is required in this design, and the demanding requirement for a specific resistance value is not necessary. Thus, using a PR to form the equivalent resistance R P of LPF2 is acceptable, which also ensures area efficiency.
The transfer function of the capacitively coupled IA of this paper is analyzed as follows. The feedback resistor R F B in Figure 3 is divided into three parts—the switched-capacitive low-pass filter LPF1, the equivalent resistance R S C of the SCR, and the continuous-time low-pass filter LPF2—and their functions are derived independently.
As shown in Figure 3a, the low-pass corner frequency and transfer function of the low-pass filter LPF1 with a switching frequency of f A are as follows:
ω L P F 1 = f A C 1 C 2 ,
L P F 1 ( s ) = 1 1 + s ω L P F 1 ,
As shown in Figure 3b, the equivalent resistance R S C of the SCR with switching frequency f B is as follows:
R S C = 1 f B C 3 ,
As shown in Figure 3c, the low-pass corner frequency and transfer function of the continuous-time low-pass filter LPF2 containing the equivalent resistor R P of the PR are as follows:
ω L P F 2 = 1 R P C 4 ,
L P F 2 ( s ) = 1 1 + s ω L P F 2 ,
The transfer function for conventional capacitively coupled IA is as follows:
H ( s ) = s R F B C I N s R F B C F B + 1 ,
where C I N , C F B , and R F B are its input capacitance, feedback capacitance, and feedback resistance, respectively. The transfer function for the capacitively coupled IA shown in Figure 6a can be derived as follows:
H ( s ) = s R S C C I N s R S C C F B + L P F 1 ( s ) + L P F 2 ( s ) ,
Because ω L P F 1 and ω L P F 2 are designed low enough and ω L P F 1 and ω L P F 2 are far enough away from the high-pass corner frequency of IA, Equation (10) can be approximated as follows:
H ( s ) s R S C C I N s R S C C F B + 1 ,
Therefore, the gain A and the high-pass corner frequency ω H P of the proposed capacitively coupled IA can be derived as follows:
A C I N C F B ,
ω H P 1 R S C C F B = f B C 3 C F B ,

3. Simulation Results and Discussion

3.1. AMP Results

Figure 7a shows the simulated gain frequency response result of the AMP in Figure 5 under various PVT corners. The gain can be obtained to be approximately 64 dB and is insensitive to PVT variations. In addition, Monte Carlo simulation of the AMP’s gain is performed as shown in Figure 7b. The gain of the AMP is also insensitive to mismatch.

3.2. IA Results

The layout of the proposed capacitively coupled IA with the SSP is shown in Figure 8. Its core chip area is 0.16 mm 2 . The capacitively coupled IA with the SSP is simulated and analyzed. In addition, two capacitively coupled IAs with feedback resistances of an SCR and a PR, respectively, are also simulated and analyzed in comparison to the capacitively coupled IA with the SSP. Note that the three structures have the same circuit parts except for the feedback resistor R F B .
The gain frequency response of the proposed capacitively coupled IA with the SSP is simulated and analyzed under different PVT corners as shown in Figure 9. The gain can be achieved at approximately 37 dB and the high-pass corner can be achieved at approximately 73.9 mHz. The proposed capacitively coupled IA with the SSP has a low range of variation in the gain and high-pass corner and has PVT robustness.
The gain frequency responses of three different capacitively coupled IAs are simulated and analyzed as shown in Figure 10. The gains of the three capacitively coupled IAs are similar: approximately 37 dB. However, their high-pass corners are significantly different. The capacitively coupled IA with an SCR has a 10× change in the high-pass corner compared to the capacitively coupled IA with the SSP, which is 740.7 mHz. Moreover, the capacitively coupled IA with a PR has a high-pass corner of 21.1 Hz, which is 286× larger than the high-pass corner of the capacitively coupled IA with the SSP. The high-pass corner increases obviously.
Figure 11a,b show a simulation of the Monte Carlo mismatch analysis for the gain and high-pass corner of the capacitively coupled IA with the SSP. The simulation shows that the mean of its gain is 37.0 dB and the standard deviation is 40.0 mdB. The mean of its high-pass corner is 79.99 mHz and the standard deviation is 6.5 mHz. This demonstrates that there is a 99.7% probability that the proposed capacitively coupled IA has a gain that varies in the range of ±0.12 dB and a 99.7% probability that the high-pass corner varies in the range of ±19.56 mHz. The capacitively coupled IA with the SSP has an insensitivity to mismatch for the gain and high-pass corner.
Figure 12a,b show a simulation of the Monte Carlo mismatch analysis for the gain and high-pass corner of the capacitively coupled IA with the SCR. The gain of the capacitively coupled IA with the SCR has a mean of 37.1 dB and a standard deviation of 36.7 mdB. Its high-pass corner has a mean of 767.6 mHz and a standard deviation of 46.4 mHz. The capacitively coupled IA with the SCR has a larger gain and high-pass corner variation than the capacitively coupled IA with the SSP and is more sensitive to mismatch. In addition, the mean of its high-pass corner is also larger than that of the capacitively coupled IA with SSPs.
Figure 13a,b show a simulation of the Monte Carlo mismatch analysis for the gain and high-pass corner of the capacitively coupled IA with the PR. The gain of the capacitively coupled IA with the PR has a mean of 32.4 dB and a standard deviation of 12.7 dB. Its high-pass corner has a mean of 36.7 Hz and a standard deviation of 13.3 Hz. The capacitively coupled IA with the PR varies more obviously in gain and high-pass corner compared with the previous two structures. As a result, the capacitively coupled IA with the PR is more affected by the mismatch.
Figure 14 summarizes the simulated high-pass corner variations of the above three capacitively coupled IAs for different PVT process corners. The high-pass corner of the capacitively coupled IA with the SSP varies less with the PVT corners, and the difference between the maximum and minimum values is only 0.06 Hz. However, the high-pass corner of the capacitively coupled IA with the PR varies largely with the process corner, and the difference between the maximum and minimum values can reach 3.9 kHz. In addition, the high-pass corner of the capacitively coupled IA with the SCR has a difference between the maximum and minimum values is 1.77 Hz. At the TT corner, the high-pass corner of the capacitively coupled IA with the SSP has a low sensitivity to temperature, with a change rate of only 0.05 mHz/°C. In contrast, the high-pass corner of the capacitively coupled IA with the PR has a high sensitivity to temperature and has a nonlinear variation with a rate of change of 32.6 mHz/°C. As a result, the capacitively coupled IA with the SSP is less affected by temperature and process corner variations.
The continuous-time low-pass filter LPF2, consisting of the equivalent resistance R P of the PR and capacitor C 4 , can filter out the spike frequency generated by the switches in the SSP. For the proposed SSP hybrid feedback resistor, it is assumed that LPF2 is removed. The feedback resistor of this capacitively coupled IA consists of only the switched-capacitor low-pass filter LPF1 in the first part and the SCR in the second part. Therefore, in the feedback loop of the capacitively coupled IA, the spike signal generated due to the sampling action of the switch is applied directly to the input of the IA without any processing. This capacitively coupled IA is still enabled to achieve a high pass corner of less than 1 Hz while maintaining the PVT robustness. However, the processed signals are disturbed significantly. Figure 15 shows the output spectrum of the proposed capacitively coupled IA (the capacitively coupled IA with the filtering of spike signals) and the capacitively coupled IA without LPF2 (the capacitively coupled IA without the processing of spike signals). The only difference between these two capacitively coupled IAs is the presence or absence of LPF2. The proposed capacitively coupled IA has a signal to noise and distortion ratio (SNDR) and a total harmonic distortion (THD) of 64.1 dB and 71.0 dB, respectively. The capacitively coupled IA without LPF2 has an SNDR of 53.8 dB and a THD of 56.9 dB. In contrast, the capacitively coupled IA without LPF2 is more affected by spike signals.
Therefore, the proposed capacitively coupled IA with the SSP has a gain of 37dB, and a high-pass corner can reach 73.9 mHz. It is more insensitive to mismatch and has PVT robustness. It meets the bandwidth requirement of physiological signal amplification, realizes accurate amplification, and ensures linearity.

3.3. AFE Results

The proposed capacitively coupled IA is used in an AFE circuit for amplification and analog-to-digital conversion of physiological signals, as shown in Figure 16. The accurate and robust amplification is realized by the proposed capacitively coupled IA. The analog-to-digital conversion operation is performed by a 10-bit successive approximation analog-to-digital converter (SAR ADC). At 100 KS/s, the post-simulation of this SAR ADC achieves an effective number of bits (ENOB) of 9.5 bits and a spurious free dynamic range (SFDR) of 67 dB.
Figure 17 shows the output spectrum of the AFE with the proposed capacitively coupled IA, which can achieve 53.9 dB SNDR and 69.5 dB THD. The capacitively coupled IA without LPF2 is also applied to an AFE circuit. The only difference between this AFE circuit and the circuit in Figure 16 is the change in the capacitively coupled IA used. The output spectrum of this AFE without LPF2 is analyzed and also shown in Figure 17. It has an SNDR and THD of 48.1 dB and 53.2 dB, respectively. Comparing the two AFE circuits, the SNDR and THD of the AFE with the continuous-time low-pass filter LPF2 are significantly improved.
Table 1 summarizes the performance of the capacitively coupled IA in this paper and compares it to various previously published IAs applied to physiological signals.
Table 2 lists the published work on various AFEs in the field of physiological signals and compares it with the AFE proposed in this paper. The proposed AFE also achieved competitive SNDR and THD values.

4. Conclusions

This work demonstrates a capacitively coupled IA using a CMOS 130 nm process for physiological signal acquisition. It presents an SSP hybrid feedback resistor consisting of a switched-capacitor low-pass filter, an SCR, and a continuous-time low-pass filter. The SSP hybrid feedback resistor applied to the capacitively coupled IA realizes an equivalent resistance of TΩ, which allows the proposed capacitively coupled IA to achieve a high-pass corner of 73.9 mHz. The high-pass corner varies with temperature by 0.05 mHz/°C and with the PVT corners, by less than 0.06 Hz, which demonstrates its PVT robustness. In addition, the proposed capacitively coupled IA is applied to the AFE, and the AFE achieves an SNDR of 53.9 dB and a THD of 69.5 dB. Signal amplification and correct analog-to-digital conversion are finally realized.

Author Contributions

Conceptualization, H.X.; methodology, H.X.; validation, H.X., Y.L. and T.L.; formal analysis, H.X.; investigation, H.X., Y.L., Y.D. and Z.L.; resources, J.Z., Z.L. and H.Z.; data curation, H.X.; writing—original draft preparation, H.X.; writing—review and editing, H.X., Y.D., J.Z., Z.L. and H.Z. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Data Availability Statement

The raw/processed data required to reproduce these findings cannot be shared at this time as the data also form part of an ongoing study.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Illustration of a capacitively coupled IA with different possibilities to realize the feedback resistors.
Figure 1. Illustration of a capacitively coupled IA with different possibilities to realize the feedback resistors.
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Figure 2. Top-level schematic of the traditional capacitively coupled IA.
Figure 2. Top-level schematic of the traditional capacitively coupled IA.
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Figure 3. Feedback resistors for capacitively coupled IA with (a) LPF1. (b) R S C . (c) LPF2.
Figure 3. Feedback resistors for capacitively coupled IA with (a) LPF1. (b) R S C . (c) LPF2.
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Figure 4. (a) Schematic diagram of PR in LPF2. (b) Simulated equivalent resistance of the PR in LPF2 against voltage variations across the terminals.
Figure 4. (a) Schematic diagram of PR in LPF2. (b) Simulated equivalent resistance of the PR in LPF2 against voltage variations across the terminals.
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Figure 5. Schematic diagram of the AMP.
Figure 5. Schematic diagram of the AMP.
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Figure 6. (a) Top-level schematic of the proposed capacitively coupled IA. (b) Timing diagram of the proposed capacitively coupled IA.
Figure 6. (a) Top-level schematic of the proposed capacitively coupled IA. (b) Timing diagram of the proposed capacitively coupled IA.
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Figure 7. (a) Simulated gain frequency response of AMP against different PVT corners. (b) Monte Carlo simulations of AMP’s gain.
Figure 7. (a) Simulated gain frequency response of AMP against different PVT corners. (b) Monte Carlo simulations of AMP’s gain.
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Figure 8. Layout of the proposed capacitively coupled IA.
Figure 8. Layout of the proposed capacitively coupled IA.
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Figure 9. Simulated gain frequency response of the proposed capacitively coupled IA against different PVT corners.
Figure 9. Simulated gain frequency response of the proposed capacitively coupled IA against different PVT corners.
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Figure 10. Simulated gain frequency response of capacitively coupled IA against three structures (SSP proposed in this work, SCR, and PR).
Figure 10. Simulated gain frequency response of capacitively coupled IA against three structures (SSP proposed in this work, SCR, and PR).
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Figure 11. Monte Carlo simulations of the capacitively coupled IA with SSP’s (a) gain and (b) high-pass corner.
Figure 11. Monte Carlo simulations of the capacitively coupled IA with SSP’s (a) gain and (b) high-pass corner.
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Figure 12. Monte Carlo simulations of the capacitively coupled IA with SCR’s (a) gain and (b) high-pass corner.
Figure 12. Monte Carlo simulations of the capacitively coupled IA with SCR’s (a) gain and (b) high-pass corner.
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Figure 13. Monte Carlo simulations of the capacitively coupled IA with PR’s (a) gain and (b) high-pass corner.
Figure 13. Monte Carlo simulations of the capacitively coupled IA with PR’s (a) gain and (b) high-pass corner.
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Figure 14. Simulated high-pass corner frequency of capacitively coupled IA against three structures (SSP proposed in this work, SCR and PR) under PVT corners variation.
Figure 14. Simulated high-pass corner frequency of capacitively coupled IA against three structures (SSP proposed in this work, SCR and PR) under PVT corners variation.
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Figure 15. Simulated output spectrum of the proposed capacitively coupled IA and the capacitively coupled IA without LPF2.
Figure 15. Simulated output spectrum of the proposed capacitively coupled IA and the capacitively coupled IA without LPF2.
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Figure 16. Overall architecture of the AFE.
Figure 16. Overall architecture of the AFE.
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Figure 17. Simulated output spectrum of the proposed AFE and the AFE without LPF2.
Figure 17. Simulated output spectrum of the proposed AFE and the AFE without LPF2.
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Table 1. Performance summary and comparison of IA.
Table 1. Performance summary and comparison of IA.
[26][6] *[25] *[29]This Work *
Year20142018202020222023
TechnologyCMOS 180 nmCMOS 130 nmCMOS 130 nmCMOS 180 nmCMOS 130 nm
IA TopologyCap-CoupledCap-CoupledCap-CoupledCap-CoupledCap-Coupled
R F B  1 TopologySCRPRPRPRSSP
Gain36.7 dB34.6 dB55 dB52 dB37 dB
High-Pass Corner300 mHz702 mHz766 mHz411.6 mHz73.9 mHz
High-Pass Corner: Max. − Min.N/A 20.82 Hz0.86 Hz2.6 Hz0.06 Hz
High-Pass Corner var. Over Temp.N/A 28 mHz/°C12.5 mHz/°C100 mHz/°C0.05 mHz/°C
1 Feedback resistance. 2 Not mentioned. * Post-layout simulation.
Table 2. Performance summary and comparison of AFE.
Table 2. Performance summary and comparison of AFE.
[30][31][32][33]This Work *
Year20152018202020212023
TechnologyCMOS
65 nm
CMOS
180 nm
CMOS
65 nm
CMOS
65 nm
CMOS
130 nm
ADC Topology8 bit SARDelta-Sigma10 bit SAR10 bit SAR10 bit SAR
CalibrationNONONONOYES
AFE SNDR30.7 dB53.2 dB50.5 dB46.3 dB53.9 dB
AFE THDN/A 1N/A 11.1%<0.146%0.03%
1 Not mentioned. * Post-layout simulation.
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MDPI and ACS Style

Xu, H.; Liu, Y.; Duan, Y.; Li, T.; Zhang, J.; Li, Z.; Zhang, H. A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor. Electronics 2024, 13, 366. https://doi.org/10.3390/electronics13020366

AMA Style

Xu H, Liu Y, Duan Y, Li T, Zhang J, Li Z, Zhang H. A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor. Electronics. 2024; 13(2):366. https://doi.org/10.3390/electronics13020366

Chicago/Turabian Style

Xu, Hao, Yunda Liu, Yachi Duan, Tianke Li, Jun Zhang, Zhiqiang Li, and Haiying Zhang. 2024. "A PVT-Robust and 73.9 mHz High-Pass Corner Instrumentation Amplifier with an SCF-SCR-PR Hybrid Feedback Resistor" Electronics 13, no. 2: 366. https://doi.org/10.3390/electronics13020366

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