Class AB OPA AC Analysis ??

[mark_nctu]

I design OPA with OTA + Class AB output.

When OPA at Vdd=5V , Phase has inverted to 180.

But low vdd (3V) is ok. Could some tell me how to

solve the problem?

Circuit:

Test_Circuit:

5V AC Result:

3V AC Result:

Added after 2 minutes:

Sorry Reupload 3V AC Result:

 

[renwl]

from the picture,When OPA at Vdd=3V , Phase has inverted to 180. right?
in the testbench,the out should has the same phase as the input.

 

[xjxmn]

There is no problem in your design, I can judge both 5V and 3V have enough phase margin just from your gain plot. You can give a step input to verify the circuit stability.

 

[walker5678]

i don't understand the test structure you showed, just try this structure, in which the resistor is 1G, capacitor is 1F.

 

[xjxmn]

i don't understand the test structure you showed, just try this structure, in which the resistor is 1G, capacitor is 1F.

I think his test structure has no problem, If he sets LDC=∞, CDC=∞.

 

[mark_nctu]

LDC=CDC=1000

Added after 3 minutes:

Hi walker5678:

Step input is stable. I try your structure. The curve is the same.

 

[xjxmn]

There's no problem in your circuit, I think you can try another tool to simulate AC respose. Maybe it's just a bug in your tool. And you can try other different Vdd in your tool.

 

[walker5678]

"VOP
DC=0"?

 

[mark_nctu]

Hi walker5678:

VOP is used to sense OPA power current.

So VOP si DC =0 .

 

[walker5678]

ok, i see.
The OPA circuit stucture is just normal, and should be OK. Some suggestions:
1. Check the DC operating point of the circuit when Vdd=3V and Vdd = 5V, to see if there is any difference, pay attention to the floating bias and the output MOSFET gate voltage. But if the circuit can work under 3V, 5V should be OK. just try.
2. Try to disconnect the load, and simulate to see if it is OK for Vdd=5V.

Hope it help.

 

[mark_nctu]

Hi xjxmn:

I use Hspice to simulate the circuit.

Thanks for you suggestion.

I will try any other vonder's spice simulation tool.

 

[mark_nctu]

I try smash to simulate the circuit and get the same result.

But change other fundry's spice model, the phase is ok at Vdd=5V.

We can be sure that circuit is stable at step input.

Maybe the circuit is ok.

Thanks.

 

[walker5678]

I think the circuit structure is OK, but the W/L size of the transistors might be with problems. Would like to know how you determine the W/L size? If the floating bias circuit was designed for 3V application, then there might be problem under 5V, because there should be cretain relationship between the foating bias circuit and the output MOSFET. If i am wrong, just point out.

Best regards.

 

[Humungus]

I guess the problem comes from either the constant Gm block or the biasing of the cascodes. I've been using this architecture for a while and with no much effor you reach gains of more than 100dB. The gains shown in the figures are a poor 70dB.

Please upload a schematic showing all transistors. Also indicate the common mode input voltage. Maybe the circuit ois not operating in its linear region. I'm prety sure the problem comes from some bad biasing.

 

[xjxmn]

From the gain plot of 5V, I can calculate the phase margin.

PM=180-90-arctg(0.1)+arctg(0.01)=84.6
arctg(0.1) for the contribution of second pole, arctg(0.01) for zero.

I think the poor gain is because the cascode transistor works in linear region, in 5V condition. Because both 3V and 5V have the same GBW, but their -3dB frequency is different. So I guess the main pole small signal resistor is reduced when the circuit works in 5V condition in your current model, my suggest is you should check your bias circuit, there should be some problem in it. But if you don't care the gain, the circuit will work stably for the enough phase margin.

 

[walker5678]

The W/L size of M3,M4, M7, M8 together with M13,M14 should be designed elaborately.