DK Kharate

OXFORD See DIGITAL ELECTRONICS : — 1 a iene KHARATE |Principal Matoshri College of Engineering and Research Centre NashikOXFORD other countries Published in india by Oxtord University Pree YMCA Library Building, 1 Jai Singh Road, New Delhi 10001 Indi © Oxford University Press 2010 ‘The moral rights of the author have been asserted First Edition published in 2010 Seventh impression 2013 Allrights reserved. No par of this publication may be reproduce, sored a retrieval stem, or transmitted, in any form or by any means win Briorpermision in writing of Oxford University Pres, or as expreninng sg by law by licence or under terms agreed with the appropriate eprooen rights organization, Enquiries concerning reproduction outside the sore ne above shouldbe sent tothe Rights Department, Oxford University recs sears address above You must not circulate this work in any other form and you must impose this same condition on any acquirer ISBN-13: 978-0-19-806183-0 ISBN-10; 0-19-806183-8 ‘Typeset in Times Roman by Pee-Gee Graphics, New Delhi Printed in India by Raj Kamal Electric Press, Kundli, Haryana Mrs Bl To my beloved parents hagirathi and Mr Kashiram KharacPREFACE 1 techniques and syst tremendous power and wefulnes of ital ncante aan vrei of applications inte areas Findus mache" cOmPUETS een com andhousehod appliances, among others. The areas whete digital aera jcscanbe applied are increasing ata fast pace. Several cial pa te ,ement skills, entrepreneurial arcmnering ails, cost advantage, project manag crea and ong customer relationships have made Iniathe prefered destination sanaraming electronics industry. This has allowed the individuals involved in ‘ero showease thei alent and meet the curent demands of the consumers sas indates. Alles actorshaveresltedin the growing interest among students and faculty members of this subject. ‘Developments inthe integrated circuits (IC) technology have made it possible tofabricate complex digital circuits such as microprocessors, memories, complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs). The emergence of various programmable logic devices has resulted in significant changes in the design methodologies of digital systems. Therefore, itis essential to have a strong foundation of the basic digital techniques for making, effective use of automation in digital design. About the Book ‘Thisbookissuitable foracourse in digital electronics and logicdesign in undergraduate ‘engineering disciplines such as electrical, electronics, instrumentation, telecommunication, computer science, and information technology. The last four ‘chapters of the book will also be useful for postgraduate engineering students pursuing ‘courses in electronics and computer science as alsoto postgraduate students of physics specializing in electronics. ‘The book presents the basic theory of switching circuits and their applications, ‘The availability of various digital functions in ICs has changed the teaching of digital electronics from the good old approach of using discrete devices to anew approach of using modern digital ICs. This book adopts the new approach. The {exthas been systematically organized and the presentation has been kept at a level appropriate for students with the basic knowledge of circuit theory and digital electronics. _ Since the study of Boolean algebra helps in analysing and synthesizing switching circuits, a complete chapter is dedicated to Boolean algebra. Separate chapters on ‘asynchronous and synchronous circuits and K-maps have also been included.ee hillutrations and solved examples Thetextis interspersed with ll vl fran Content and Structure ed into 1Ochapters. A brief descriptioy diode transistor logic (DTL), modified diode-transistor logic, transistor-transi ‘ ed logic, integrated injection logic (121) Nag eestor cl ctailed study of different aumber systems, thing Chapter 2 includes the detailed study of > i conversion, binary arithmetic codes, eor detecting codes, and error comecting cae Clap 3 udes Bocca lebra, DeMorga's theorems, simplification Bolen expression by algebraic method, Karmaugh map metho, and gn MeCluskey method. Chapter 4 ls with combinational logic design using MSI circus, which g impr fr the dein of digital systems considering the simplicity in des cost, space, power requirement, speed, and other factors ‘ater inte he basi builing blocks of sequemal ruts including ip. TePconversons application of flip-flops, shift registers and ther application, Us chapter also discusses the analysis and design of synchronous sequentel ciruit Chapter 6 iscuses the analysis and design of asynchronous sequential circuits Chapter 7 discusses various ways of representing the control sections and data ‘cations of hardware algorithms. The chapter includes the use of algorithmic state machine (ASM) charts, register ‘wansfer language (RTL), and covers the hardware ‘description language, VHDL, ae ‘Programmable logic arrays (PLA), programmable array logic a ). generic aray logic (GAL), ‘complex programmable logic device (CPLD), ariemable gate amays (FPGAs), Xilinx XC 9500 CPLD family, and 4 fic imegrted circuits (ASIC), ‘hapter 9 ex, é Pains the mos common A/D and D/A conversion techniques. Chapter 1 Hapler 10 presents the Sindy of memory organization. and operations, classification, : EEPROM, stink Wo memories—RAM, ROM, EPROM, vite astra g this project. First ivi aceite mary il wn ed ne rings oe Fu and Pujn-tom vom Lrcsved cx ascaragecst mt ODDS nega ce for this endeavour and no ‘Ther fovingandcring ait hasbeen the driving free forth ende tude to Dr (Mrs) words of gratitude are enough. Ialso express my deep sense of gratitude to Dr( Saree oe : Ss ment, and undying enthusiasm throughout this project. I wish to specially thank ¢ with my research thank Po D:D. Dighe and MrH.D, Deshpande who helped me with Spel ato my prasad ther fox hk wooo e c riends, relatives, and colleagues love and support. Thanks are also due to all my friends, ees for their suppor. Finally, I thank the editorial team at Oxford University Press, Delhi, for their cooperati Dr G. K. KharateCONTENTS Chapter 1: LOGIC FAMILIES 1 1.1 Introduction 1 1.2 Logic Families 2 1.3 TransistorasSwiteh 3 AA Characteristics of Digital ICs 4 | _1S Resistor-Transistor Logic (RTL) 8 ~ L6 Direct Coupled Transistor Logic (DCTL) 9 “1.7 Diode-Transistor Logic (DTL) 17 poeee ~1.8 Modified Diode-Transistor Logic 12 a ~1.9 Transistor-Transistor Logic (TTL) 13 1.10 TTL Parameters 23 kA vsleie ae 1.11 Commonly Used ICs of Standard TTL 26000 1.12 Improved TTL Series 27000 1.13 Comparison of TTL Families 290 1.14 Emitter Coupled Logic Lis28 Arithmetic Overflow 91 Flop 306 BP ais 5.8 Characteristics of Flip-Flop 3 ce 5.9 Flip-Flop Conversions 307 c : SRA LOGIC GAT 5.10 Applications of Flip-Flops 32 chapter: BOOLEAN ALGEBRA Al a ie SOE Ca aaa 5.11 Registersand Shift Registers 427 tof Shih egiter 24 12 Basen Alghen129 512 Aplin of Shi 5 5.15 SynchronousCounter 355 5 Standard Representation foe Logical Functions : priveril oped i 5.16 Flip-Hlop Excitation Table 335 chat 5:17 Synchronous Counter Design 358 27 Sri seed Ho 31 eae ira os teem 5.19 Clocked Sequential Circuit 369 so ou ee ee $5.20 Analysis of Clocked Sequential Cieuit 371 eee .21 Design of Clocked Sequential Circuit 375. 3.11 Five- and Six-variables K-map 87 : a a 5.22 Lockout Condition 398 3.12 Quine-MeCluskeyMethod 185 iS At Rea Chapter 4: COMBINATIONAL LOGIC CIRCUITS 198 Oe ee 4.1 Introduction 198 Chapter 6: ASYNCHRONOUS SEQUENTIAL CIRCUITS 431 42 Design Procedure for Combinational Logic Circuit 199 6.1 Introduction 437 6.2. Fundamental Mode Asynchronous Sequential Circuits 432 6.3 Pulse Mode Asynchronous Sequential Circuits 440 6.4 Incompletely Specified State Machines 447 6.5 Problems in Asynchronous Cireuits 449 6.6 Design of Hazard-free Switching Circuits 452 43 Adders 202 44 Subtractor 211 45 BCD Adder 219 4.6 BCD Subtractor 220 4.7 Arithmetic Logie Unit 226 4.8 Comparator 229 49 Parity Generator 233 4.10 Patty Checker 235 4.11 Parity Generator/Checker (74180) 239 4.12 Multiplexer 247 413 Demultiplerer 257 4.14 CodeConverters 264 4.15 PIN Diagrams of ICs 286 Chapter 5: SEQUENTIAL LOGIC CIRCUITS ‘5.1 Introduction 293 5.2 I-bitMemory Cell 294 53 Clocked$-R Flip-Flop 297Chapter 9; Chapter 10: Index 86 Complex Progr 8.7 Field Program . 1b 8.8 Application Specig, AMD AND D/A CONVERT, 9.1 Introduction sy 9.2 9.3. Basie Principte 9.4 DACand aDCIe, 9.5 ADCO809 (8.pit ADC) 6599 9-6 ADC-7109 (12-bit by 9.7 DAC 0808 (8. it Dac)” AO. on Locic Fami.ies SEMICONDUCTOR yy 10.1 Introduction 639’ MORY PEVICg, 10.2 Memory Organization 630 val Diagram of Meno, Chapter Out! vreceenmeeecrarre 5 of og arin Bah charac fran Charactoistes of dal Ios ‘+ ATL, DCTL, TTL, ECL loge famios i + OMOS NANO, NOR and invertor 10.6 Characteristics of Memory Devices + Comparison of TTL and CMOS 10.7 Classification of Semiconduety Mend ‘tert Cvs endcosin 10.8 Read and Write Memory 644 C + intoracng of TTL {7a oe tae 10.9 ReadOnly Memory 652 ies "Y 63] 1.1 INTRODUCTION ekcgencemed with te inercomec on among digi Components systemisthey a _ sent , “ smmable LogicDevices 557 46 Complex Pr 7 Field Programmable m Specific ‘Gate Ary Fmepatd Circuits (ASICS) 561 ss Appia |p ANDDIA. CONVERTERS 584 91 ten 3 32 osicPrinipleofDAC 58 33 Basi Principleof ADC 59% 4 DACand ADCICS 495 ADCOSI (8-bit ADC) Be ape-7109 12-bit binary ADC) 61! 9.7 DACOSOR bit DAC). 626 Chapter 08 630 caper: SEMICONDUCTOR MEMORY DEVIC Tout Iniroduction 630 10.2 Memory Organization 630 10.3 Functional Diageamof Memory 631 Jot Memory Operations 632 1015 Expanding Memory Size 635 1066 Charactersicsof Memory Devices O47 10.7 Classification of Semiconductor Memories 642 108 Readand Write Memory 644 10.9 ReadOnly Memory 652 Indes i Chapter | — Locic FAMILIES == Chapter Out!ine ‘= Types of logic families + Switching characteristics of + charactors of ait ICs ATL, OCTL, TTL, ECL logic families {+ CMOS NAND, NOR and inverter + Comparison of TTL and CMOS + Interfacing ot TTL to CMOS and CMOS to TTL * inieriacing of TTL to ECL and ECL to TTL + 74X% series data shot nsistor 1.1 INTRODUCTION Digital fogiisconcerned with the interconnection among digital components and ‘modules, The best known example of adigtal system s the general purpose digital computer. Most ofthe digital cireuits are constructed om a single chip, which are refered to as integrated circuits (IC). Integrated eieuits contain a large number ofimerconnectd digital circuits within a single smal package ‘inl scale integration SSI and medium scale integration (MSI devices provide electronic components ina eas varity of forms and each form is referred as a ‘Now-a-days digital integratedcircutsare most i systems ICs ae popular duo eircnomous advanagehaslitetelon. © * Smallinsize rea + Loweost oe Olan pied cone2 _ Distal econ i" + High noise 1 high ity = Hignseod ecudes testy of diferent og ss ude shot of commonly sed eres 7AXX families, interfacing of logic 1.2 LOGIC FAMILIES ‘The setofcompatibe ICs with he sume logic levels and same supply voltages have aa ete eee ee finctons known eso fail. Based Unipolar kg family Inno logical, unipolar devices arth key element. MOSFET (Metal vide Senicontctor eld Eet Transistor is unipolar device in which caren Tvs hecase of only one type of charge ci (hat, either elestons tots). Theexamples oF utpoa ane include PMOS, NMOS, and CMOS. Bipolar logic family Transistors nd diodes ae bipolar devices, in which the current flows because of Jeuhthe charge cares (lecton ado) Inipoa loi fanilies, tasistors an diodes re ased as key clements On the bss of operations of transistor in 1Cs, bipolar oie fun are arr classified as + Swurated bipolar logic families * Unsaturated bipolar logic families ‘ns bipotar ogc fails, transistors operate in saturation region The speed of stud bipolar ogc fails low, easns of which would beisessed inertcoming topics, Examples of strated bipolar ogc fares at * Resitorunsistorlogic * Direct coupe ranssor logic + Integrated injection loge + Dioweansisor logic + High-reshold ogc * Trunistor-ansistor logic 1 Schotthy transstor-transsto logic * miter coupled logic 1.3 TRANSISTOR AS SWITCH _ tana ogic families. It Tranitr isonet si ror sation region. The cto sane lich OFF and saturation refered a8 switch ON. sah waar, which x neta ncolcr neon aren forwaia Stnterjunton sa andvotage across emiter and collector terminals is Vea Teva "08 Vrain waristoran0.3 for german si Theat Viz~0. foralcortanstorand01Vforgemaniontani ae ey bec be taelorin sraon tha the base curent abou! eign tay he colstr erent Ata i > Te clo ucaiar working «Betis Ua sg ‘operates as aswitch. In Sotto eered tas switch inthe eva region, bth eit condition and only reverse erent The saturation region, borne Fig. 1.1 Transistor asa switch ‘When input Ve applied to the transistor is LOW (0 V), the emitter junetion is seers biased, thes curent Mowing through the base terminal andthe cure lowing trough the collectorierninalisreversesaturationeurrent, whichis By applying KVL to the output loop, es Veo =1eRe=Vaa=0 Vou = Vor = toe ay Tn the cut-off region, collector curent Fe Hai a2) Wen the transistor is operating in et : : refered to a8 HIGH (logic 1) off the output i equal to Vee and itis ‘When input Vj that is applied tothe emitter Janson s forwarded caren flowing trvghtnete ie ee i ta sc e-card there isa consi tuput voltage considerable voltage drop across thecollectorresision Ad Vou Veta ) ‘When the transistor is operating itisreferedio asLOW (logic), by the input voltage,Fig. 1.2 Response of transistor switch for square wave input entries ro OFF ON ste he char i state condition. Similarly when it switches from ON to time to each the OFF sate, the excess Turn-ON time Isto time req ges fom low thigh are stored must be removed which takes sometime wired to each the steady stat condition when the input ch tows tett aa) where vis delay time and is time Delay time sthetime equi oe the collec ofthe maximum value of the elector current Ort neither forthe coetor cure tris from 101090 percent ofthe maximum value of the collector current Ft isthe ine equio move the exes care sored near the Junction, when the inpt changes from high to low Yorcurento rise fromOto 1Opereent fone + (sy wheres fll time an is storage time, Storage tine {zie time requited o drop the collector current 1090 percent of regs value of the collector curtent when the npun ‘changes from high to low. Falltime mn ered rope colledorcurent fom S00 deren ‘of the maximum value of the collector curen, 14 CHARACTERISTICS OF DIGITAL Ics et i tin of lyr ple items neni einen "Snares meen ny etre NB epee ep be per aE - sal a * Powers og Faniie + Figure of meri + Fun-out + Fania * Current and voltage parameters + Noise Immunity * Power supply requirements * Operating temperature 1.4.1 Speed of Operation npceiaind apron of ig 1x hae ih 1 ied nt propanol tins Ista seraga the propepulon ay Hi iow sate GW high vat fou. + ton. (1.6) ightotow state, bere asthe ly ime measure, when ouputchanges fom igh ieee ees oe ae ae aa hse The pat nd ouput votage waveforms of age gate ae show Fi 1.3 Input and output votage waveforms of logic gate ret ay limes are measured between 50 percent voltage levels of ‘input and ‘output waveforms crnyeroreeation delay between input and output should be as ‘minimum as Pesibleso tha the operating speed of IC remains high, 1.4.2 Power Dissipation terms of mili Watt mW), 14.3 Figure of Meritital sectonis if sit sa roduc of propagation delay and poy Figure of mei it Joules (ns xmW = pl). POE sored ners of PICO poms Ssipaton ese Parameters rrentand Voltage _ srs defnetbenimum and maxiaum mit of cure Cuenta volar Cae ong nd opt oF gic fail td voltae fring res Tighe! iat age) ste minima inp volage conespondin log ste. 1 don eel pave) este maximum ipotvolage corresponding ty epic tte Ve ih evel cpu volage) iis the minimam ouput voltage corresponding to lope a. Voq(towlevloup votage) isthe maximum ouput voltage comesponding tp logic ste (igh evel ip caret) Ms the minimum input curtentcomresponding to tan denied at cere Xs sit set one trina Macoracontenduatnsset eee Pe Iota tides ars OSHC 1.4.5 Fan-Out Fact ci esg : fee few dive he maximum name of sr = ‘High fan. ‘utis advantageous, because itreduces the need of additional : rive more gates, Consider Fig. 1.4, os Ie Ae drpacat e Logic Families Fou. tox. a7 1.4.6 Fann 5: Fan-in is the number of inputs toa gate. Fora two-inputs gate, fan-in is two; an fora four-inputs gate, fan-in is four. 1.4.7 Noise Immunity Unwanted signals are known as noise, The stray electric and magnetic fields may induce some noise atan input of digital circuit. Because of noise, the input voltage ‘may drop below Vj ormay be aise above Vi, which resultsin undesired operations. ‘The circuit should have the ability to tolerate the noise signal. ‘The noise immunity of digital circuit is defined asthe ability of a digital circuit to tolerate the noise signa. A quantitative measure of noise immunity isknown as noise margin. Logic | state noise margin and Logie O state noise margin can be calculated as: (1.8) as) Vou~ Vin Logie | state noise margin A\ Logic 0 state noise margin AO = Vn, = Vou, 1isimportant that fr logic families, Vy,> Voy and Vi, > Voy as shown in Fig. 1.5. Yu % You in ar npr voltage level Fig. 1.5. Input and output voltage levels Tit gate has Vou = 24 V, Vou. = 04 V, Vi =2 V, and Vi, = 08 V. The tkeLogic Families sawch thatthe ovtput OF 8G; iS in Logie g | See ae cia ae oe i tum current lows etc amt | > When he transistor operates in saturation region, maximum current Paws etme Valent Vw (ig, throushresstor The output voltage Vy= Vena Vera 0-2 foraltcon 2Vq-04 perates cutoff, no current flows through resistor Rcand the output voltage Mei tes 0.8V. When the nose intr Vp =Voo= #5 Vr itis logic | level voltage. ‘ «When oth the inputs ae in logic 0, transistors T and T; operate in cut-off, yw level inpat ofthe 84 re ye. bet po te oe igptleveland the output will intl put willbe unpredcane output of Bey ‘Themaxinum 0 the sini reset hands Vwhchinasis and the output is +Vec, ie. +5 (logic 1). + When any one ofthe inputs is at logic I level, the corresponding transistor ‘operates in saturation, and the output is Vy = 0.2 V (logic 0) aye Va=24- Vat «When to th input a a Tope vel, both the transistors operate in Voaue #24 = Vo saturation and the output is V; = 0.2 V (logic 0). The operation of circuit is Somme in Table (0. ‘heminommbighlevelinpoto te gateis2V, When the noise signalis prea (AV, theinputof gate willbe less than 2V, which transis iggy Table 1.1) Operation of RTL NOR gate (Fig. 1.7) thn 24-2 JP iat state andthe ourpot wll Be unpredictable 5 Ve Vp [Transistor Ty [Transistor Fy 1.4.8 Power Supply Requirements a ee ery etic requires supply voltage to operate. The required su i ri ‘ollag and power bythe C shouldbe as less as possible. aly Logie 0 | Logie 1 Cutoff Saturation Logic 1 | Logic | Saturation Curott oie | topic | Saturation Saturation 1.4.9 Operating Temperature (n the basis of operating temperature range, the application of the ICs will be kidd. The operating temperature isthe range of temperature in which an IC functions propel, Its in order of 55°C to +125°C. The accepted temperature eee Comsicn SLRS Sean neon 70 fo comme annul pions, Selection ofpaicullopc family forapartculer application depends on th Latwlemehot be pean nn emanate Param, Interms of 0 and 1, the above table can be written as in Table 1.1(b).. RESISTOR-TRANSISTOR LOGIC (RTL) RTL consists of resistors and transistors, An RTL, transistors operat eee ‘ Be : SS ae Fig. 1.7 acts as a wo-inputs NOR strain reglonas pe the input volage applied. Figure 1.7 shows the enn a eters “ oma: a listed |. Low noise margin (Typically 0.1 V) 2. Fan-outis poor (Typically ) 3. Propagation delay ishigh: ‘4. High power dissipation (15 ] a ¥ Fig. 18 Twornputs DCTL NOR gate a career both te iapets me inlopicl, hecoesponding wansisor or tansisions ee ers Current hogging problem Figure 1.9 shows DCTL gate driving a three-inputs NOR gate, ki "519 OCT gate diving the theeinputs NOR gate | Initially the input of tan : loi 7, ots ncaa sg 28 and thei esa opie Veg ope cae This | the input of 7 chanpaataey erase } of teva gta ere | ‘Vand 0.78 V, respectively. When the voltage at the outpot of driving gate reaches O.BV, Ty goesin sat ‘The whole current flows through the base of 7% and the transist ‘Once Famages, 73 goes in saturation and will notallow other transistors toenter in saturation, The whole current flows through the base of Ts and it may damage. Similarly ll the transistors ofthe driven circuit are damaged. Itis known as the ‘current hogging problem. 1.7 DIODE-TRANSISTOR LOGIC (DTL) ThecircuitofaDTL consists of diodes and transistors. Figure 1.10shows the circuit ‘of a two-inputs diode-transistor logic NAND gate Fig. 1.10. Twouinputs DTL NAND gate Operation * When the transistor operates in saturation, the, the output voltage Vio)= Verar= « Q2¥.and wen topenes incu heoupuvalige Vena Voce 1S, Fonear ets inputs rein ogc 0, y= Vez =0.2.V, the input diodes are see. volage at point xs Va= Vo + Vp =02 + 0.7 =0.9V which at point naar n@ttvethetasistorin saturation because the voltage deseed 2107s Osea tansisor in saturation shouldbe Vasa Vna + Vin 08+-0.7+0.9=2.2V. The transi i oe “ansistoroperatesin cut-off andthe output voltageDigital : ne circuit is summa in of DT Je 124) Operon of Diodes rized in Table 1.2(a), L NAND gat (Fig. 1.10) bl x y sd based | Forward bi ad Tome evra | Reese bated | Cutt Lone || peered Pe vse biased | Forward biased | Cutoft | Logic + | | 1 | Logic 0 | Reverse ss tage e biased | Saturation | Logie » | Interns of 0 and |, Table 12a) can be written asin Table 1.2(b), {able 1.26) Operation of OTL NAND gate (Fig. 1.10) A B s | 0 0 7 | lPesgr 1 1 ° 1 eS Lo OO ‘Thecircuitshown in Fig |.10 acts as atwo-input NAND gate and Tablel.2(b) shows the truth table of NAND gate. Following are the advantages and disadvantages of DTL over RTL. Advantages 1. Fan-utis high 2. Power dissipation is 8-12 mW. 3. Noise immunity is good. Disadvantages 1, More elements are required, 2 Popsetion lay ismore(ypically30ns)andhence the speed of operation isles, 8 MODIFIED DIODE-TRANSISTOR LO‘ More fan-out gates are ‘safmetion ofsourcec ‘hecurent supply ofthe Preferred for most of the applications, Fan-out of the gate urent. The fan-out of alogic gate is increased by increasing # gate (souree current), When the base current of a transistor Logi Famties_ SS 1.11 Modified diode transistor logic 9 TRANSISTOR-TRANSISTOR LOGIC (ITL) Transistor-ransistorlogicis one of the popular saturated logic families, Transistor isthe basic element of this logic family, which operates either in cut-off or saturation region. The frst version of TTL is known as the standard TTL. Standard TTLs are available in various forms: 1. TTL with passive pull-up 2. ‘TTL with totem-pole output 3. TTL with open collector output 4, Tristate TTL, 1.9.1 TTL with Passive Pull-Up Figure 1.12 shows two-input TTLNAND gate with passive pull-up. Transistor, ‘has two emitter terminals. These terminals act as the inputs of the gate, thats, input ‘Aand input B. The input voltages are logic Oorlogic 1, where logic O corresponds to 0.2.V and logic 1 corresponds 1045 V. Veo=+5V tee Fig, 112 Twovinput TTL NAND gateAan. arein on 0, Y= Vera =0.2V, the ee Orne ico + When bot the inputs ( ions of transistor T) a oo 8 o junction is 4 Vgp 0.2407 =09 V. The minimum yon wanton 7 Fin= 10 hat T, and 7; start to conduct, is Vg, SE ra bebe of : isla i so. = 1 VT reed voles gre Va 4 nce Tp and Ta allabe atthe base of 7; and hen are in cutofy she volag avai Pee Lisle ae at varvakage sequal othe supply voltage Vec logic | level cup im gic Ista «ee ay one of the inputs isa logic 0 evel, the Corresponding emi When an oe ormardbiasedandthe voltage a the bas of Tis Vy, jen 107 =09¥. The minimum voltage required at the base of oa cot 7 eit wtoncie, Valen oy + Vat oy + 0.7 = 0.50.54 Brn FA the requted voltages preater than the vollage available ate pacofTandhence Ty and, are incu-off and the output voltage is quad reine sappy volage Voc outpatis in logic | tate + Whonallthe inputs rei ogi state, theemitter junctions of 7) are reverse biased andthe current supply by the sources sufficient operate Ty and, insaturaton andthe oupat isin logic stat ‘The operation ofthe circuit is summarized in Table 1.3(a). Table 1.1a). Operation of TTL NAND gate (Fig. 1.12) Tapas Transistor Ty Transistors | Output aoa Emitter Emitter | T;and T, junction A_| junction B Logic 0 | Togic 0 | Forward biased | Forward biased | Cut-off | Logie 1 Logic 0 | Logic 1 | Forward biased | Reverse biased | Cut-off | Logic 1 Logie | | Logie 0 | Reverse biased | Forward biased | Cut-off | Logie 1 [topic 1] Logic 1 | Reverse biased | Reverse biased | Saturation | Logic 0 | terms of Oand 1, Table 1.3(a) can be written as follows: Table 1300) Operation of TTL NAND gate (Fig. 1.12) Ya Ve % 0 ? ' ° i ip 1 is i Lt iio 0 Thecircuitshown in Fi is given in Table 1.3, Passive pullup ‘When both inputs are capacitorof ded gat change tologie ' |12actsasatwo-input NAND gate andits ruth table biased and 7, towards Voc: ese Tames _ AB Fig. 1.13 TTL with passive pull-up “The capacitor ofthe loaded gate is pulled towards Vec through the passive component Re, and hence the circuit is known as TTL with passive pull-up. In TTL with passive pull-up, the time constant is Re, x Co- The speed of the circuit can be improved by decreasing Ry, which decreases the time constant. By decreasing the value of R¢,, the power dissipation will go up due to the increased collector current of transistor 7. This problem of TTL with passive pull-up is ‘overcome in TTL with active pull-up. 1.9.2 TILwith Totem-Pole Output Figure 1.14 shows the circuit of a two-input TTL NAND gate with totem-pole ‘output, It is possible in TTL to improve the speed of operation by reducing the time constant without increasing power dissipation with the help of active pull- up. TTL with active pull-up is known as TTL with totem-pole output, Voo= 45a ———— is Vor m* Vi NS i cis greater han the voltage available ye gro? 5V. The required voltage is 21 ie availabe ay Yee (loge 1 level), output sink supply voltage Voc (lo r torreon becuent sappy he source Voc OU Reise tt ‘Tyand Ty sat t0 cond I state. Singg 0 to operate in saturation « When any one ofthe inpts is at logic O eve, the corresponding em juntion of, is forward biased andthe voltage atthe base of 74 et Vjp + Vgq=0.2+-0.7= 0.9V. The minimum voltage required at he so that and Ty start to conduct is Vatu in + Vat in + Oop ed vollgeis renter than the volageavaige and, tein et off andthe output vane of sngea7= tv. The re sete tue of, eat he isaqualto te suplyvliage Vee (ope level output inlay Since Tis ineut-of region, the current supply by the source Vee thrones = Simnde rexbeia go aoe detested nae hinedanbecueatupry bythe souls siento operas Tea insaturation and the output is logic O state Since T3 is in saturation region the voltage atthe collector of 7, is ow and T, operates in cut-off. The operation ofthe circuit is summarized in Table 1.4(a) Table 1.4) Operation of TTL NAND gate (Fig, 1.14) i Transitory [Pranttors] Transistor] apa | 4 ] B Emitter | Emiuer | T;andT,| 1, Junction A | junction B [Levco Lsico| Forward | Forward | Curoft sam fost] Roce | Sis ace toric of togic1 | Forma | cu vere | Cutott [Saturation {Logie a Pied fast a ox Lge 0 Rene | Foon | Cutot fsutuaion [Logi viased viasec : [tees fener Ase |e aa a Ll biased biased Se Interms of terms of and 1 Table (a) can be writen asin Table 1.4(b), Table 1b) Operation of TTL NAND gate (Fig. 1.14) Logic Famies _ 972 Active pullup When both the inputs are high, T3 oper nd T, operates in cut-off. The current provided by the load is sinke of the loaded gate is charged up 10 Versa logic 0, the corresponding goes into cut-off and, rates in saturation region, Vo bby Ts the capacitor ‘When one or more than one input changes to emitter junetion or junctions of 7 are forward biased. 7 {isin saturation and the diode D is forward biased. The eapacitor ofthe loaded gate starts charge towards Vcc through Ty and Dy as shown in Fig. 1.15 The capacitor of the loaded gate is pulled towards Voc through the active components [and D,. Hence the cireuitis known as TTL with active pull-up. In totem-pole output, Tact as an emitter follower. The outputimpedance of emitter follower is low. This means that the output voltage can change quickly from low state to high state. ‘When the output changes from high o low, Ts operates in saturation and the capacitor of the loaded gate discharges quickly through 7. Due to the current spike problem, wired-AND connection must not be used for totem-pole output circuits, as discussed in the next section. phcc = +SV, Voy = Vnesau + VoraLogie Families ee senceofa dod, the voltage required atthe base of 7, sy Intheabse that aan, conducts ota) ‘ 02405=07V 2 Teagan of 7 seater a he og rug and 7 rein saturation. To avoid ths situation, dag hence both T; and 7, ti D, #8 Used in ye Iermenfaie eons ind atc OT, ean toconduct, is ¥a,=Voo* Vo+ Vita cay aa ucla Fig. 1.17. Two:input modified TTL NAND Thevolagavalsble atthe base of 7; isesthan he Voltage required and ce J 7 isoperatng in cut-off. aan ae ‘The circuit ofa modified TTL. with aclamping diode at input is shown in Fig. 1.18. ghecn1V Sink current Uishecurensuplidby the load. Figure I. 16shows atwo-input modified: NAND gate driving a similar gate a When both the inputs ar in logic 1 state, 7; operates in saturation and Tag Cutoff. The output of the driver gate is logic 0 (Vo 0.2.V), the emitter junction of wansistor Tot the loaded gate becomes forward biased and the ‘current supply J = : ¢ z z z Fig. 1.18 Modified TTL with clamping diode at input Clamping diodes are commonly used in TTL to suppress the ringing caused because ofthe fast transition found in TTL. Atnormal input signal, the diodes are reverse biased forhighas wells low voltages, When transition occurs, the reactive component associated with the load causes ringing as shown in Fig, 1.19.a ee 20 Disita Electronics Les transistor may be damaged. The oes) connected the np orga, for negative spike and mits the voltage up to -0.7 V and protects ey eB anise 1.9.3 Wired-AND Connection Ar AND cometon has wo or mor thntivo gates connected pee, 4 wired-AND connection, the fami of the circuits increase er Using i>, 2 }—se 11>) T CP 5 4 Fig. 1.20. Wired-AND connection ‘Here the outputs of two NAND gates are connected together. =h¥, Y= 4B Hence ¥ = AB.@D Using De-Morgan’s theorem, Y= ABCD ‘ant Wied-AND connection i not possible in TTL with totem-pole output Thy fat diagram of wired-AND connection for TTL with totem-pole cup shown in Fig. 1.21 F121 Wited-AND connection for TTL with totem-pole ‘output aa the cutpt of gate is high and gate, is ow, then T, of gate; operates in Of gate; pense Ptses it saturation, 7; of gate, operates in saturation and Ty 2 Tsofgae ut load current and the current supplied by Voc of 2 fow though mst nt be ne eg? Tscanbe burnt out, Hence, wed: AND connection i i a Logic Famites (21 is overcome in TTL with open collector output. Figure ‘TTL NAND gate with open collector output 1.22 shows the cireuitofa emia Fig. 1.22 TTL NAND gate with open collector output The collector tenminal of 7; savailable outside the IC where the external resistor is to be connected. The circuit acts as a TTL with passive pull-up and hence the advantages of active pull-up cannot be achieved in the circuit but wired-AND connections possible. 1.9.5 Unconnected Inputs of TTL ‘The input circuit of a TTL is shown in Fig. 1.23. ‘When the inputisin logic state, theemitter junction is forward biased and the current flows through the junction. When the inputs se inlogic | state, theemitterjunctionisreversed a biased and the current cannot flow through the junction. If any one of the inputs of the ‘TTL gate is open, then the corresponding 2 “ Junction cannot be forward biased, and the currentcannot flow. The input acts exactly in thessame way, asin case when logic lis applied to that input. Therefore in TTL ICs, all ‘unconnected inputs are treated as logical 1s, Fig. 1.23 Input circuit of TTL 1.9.6 Tri-state TTL in high state or low state. Ifthe o high state. The tri-state TTL hi impedance,aati sin high-impedance state, i ° When the output i a tee 33) (0 High wpedance [ves ish fig. 1.24. Tristate logic state inverter Frecnnt ofa st TL inverter isshowa in Fi. 125 The citi. Fig. 1.25. Tristate TH inverter ‘The estate TTL inverter aswo inpus—normal input A and enable input * When te cableiapu is High, the comesponding emitter junction of {teres biased and the circuit operate asa nomal inverter as explained below input, the diode Dai flows through the outputs ini Logie The logic symbols forthe active high and active low enable input inverters are shown in Figs 1.26(a) and (b), respectively (ae Yet Ss = > ly joes zeo——] Eo. Fi. 1.26" Enable inp inven () Active low enable input Application of tristate logic ‘Tri-state buffers play an important role in computer systems. In ease of 8085 microprocessor all the buses are in tri-state whenever the 8085 isin reset mode. Figure 1.27 shows the common bus connected t four output devices, where A, 5, Cand D are the enabled inputs of tri-state buffer. Data present over the bus is Evento the device a per the enabled input signal ofthe tri-state buffer The enabled signal of the input device is active low : 1. isenabled and others are disaby borate veikeieis piven todevice wen ao ceoet vento denna and thes ae disabled, andthe ee pee OS C= LD: sive todevice2.Whend =1,B= 1, Ccorn ay Gable andthe data presentovertheliens, =1.C=1,D=0, butter Disena over the lini givento device 4 eSDigital Beetonicg EDs neti En jof operation i pape anit tems of Dopagation dla sped f oe ra the prepaon ely tne 18.5 15429 stn = Smt n= 7218, tent, = 9222 2 18 5g Power dissipation sf the wastage of powering isi Hsould 3 minimum fost Fora Sandard TTL power dispation 19 mW. ma Current and voltage parameters Via: Its the minimum input voltage to be recognized 28 logic I state, Viz # Its the maximam input voltage to be recognized as logic 0 state, Vou: Itis the minimum output voltage corresponding to logic 1 state Vou. : Its the maximum output voltage corresponding to logic 0 state For a standard TTL family: Vin=2V, Vou=24V, Vi 8V, and Vo =04V sy eS av, 24 | Mu losv You—$—oav k ot ov Input vote eae Fig, 1.28 Voltage range for TTL Fig. 1.29(@) TTL sinking the current from n gates ‘When the outputof the driver gateishigh, 7, acts as a current souree tothe load as shown in Fig, 1.29(b). Ifn similar gates are connected at the output, then the ‘ota source current must be equal to times the input current Iya, where ni the fan-out of TTL. Jou = hy i n= fo. M0UA _ 19 bee tu 40UA 1jit cits imu is iy ofa its ability t0 tolerate @ noise signg mown as the noise margin, SLA ae margin (AO) = Vi. Vou sass SS. (a=08V-04V-=0.4V ature range voltage a rer he examples of standard TTL logic fail The series andthe 54 seis Tresesries pero POne™ St Zoos vk ell ove trae erie range 445 10455¥. “The 4srescan od the Series can workover emperatr Summary of standard TTL sappy voltage of+5V. But its found that they W.75V to +5.25V and the 54 series operas elaly over empeature range of °C t0 70°C, while nperature range of - 55°C to +125°C. “able 1 summarize the typical values of standard TTL parameters, Table 15 Typical values for standard TTL parameters (harctertis 7 series ‘Supply voluge | 475V 0525 V ew IC | Tepe ne | vse Coma] | | Pome sition | Pronaation dey Frat Noise margin 45V0S5V = S5°C to 125°C Vin = 2 V. Von Yu" 08, Vou y= 40 WA, fon = 400 wa 54 series 6mA, fo, = 16 mA 10mw 10ns 10 04 | Logic Families 27 Table 16 Cormeniy use I of sandr TL Te naib] —_‘Desrinnon [IC umber] Deseripion | Tait Tipe Sinpts AND pts | 7400, Ges 2ops NANG en J too [nat inp NOR ses | 7420 | Dus apts NAND st oe eee ee 7404 7408 | Quad 2-inputs AND gates | 7432 | Quad 2-inputs OR gates 7410 _| Triple inputs NAND gates} 7486 1.12 IMPROVED TTL SERIES TTL S4seres74 eres arth most popular and commonly used series of digital ICs These series have the limitation of speed and power dissipation. These limitations are overcome upto a certain limit inthe improved TT. series. The improved TT. series areas follows: 1. 74L series ow power TTL) 2, 74H series high speed TTL) 3. 148 series (Scot TTL) 4. HLS series (low-power Schottey TTL) 5. T4AS series (advanced Schotky TTL) 6. 74ALS series (advanced low power Schottky TTL) 7. TAF setes (fast TTL) 1.12.1 Low Power and High Speed TTL ‘The 74L series were develDigital Electrons is obtained by using « Schottky barrier diag, > Logie Families 9261) The Schothy transis nals of the transistor as shown in F Me sae he collector trina shown in Fig. agg," ae ee ove asa forward based voltage ef 025 Becauseofiy FAMILIES thease andthe collector terminal ofthe transistor, the cope ‘A comparison of TT anlieswithrespectto their common characteristicsisziven Reese not get forward biased and the transistor never Ja amor opeaesincu-ooractverezion. The symbol gr 88 Table tannors shown nF. 130 a Table. 1.7 Comparison of TTL families [Character- | 74 74LS 745 | 74ALS| 74AS| 74F 2 te istics fete, Meciane| “208 | 208 | 208 | 208 | 208 | 208 a Mia Jon | -0ris | -oan6 | 1720 | -oane | -200 | -120 i Nowy | soe) soi) | 20 02) | 0212) | 201-06 | Tyas) 10 3 4 1s 25 e PD. per gate| 10 20 1 20 4 » & F130 Scho transitor and Schoty symbol The 748 sts isan example of Schothy TTL. The propagation delsyqy | 4,44 EMITTER COUPLED LOGIC Schothy TTL is 3 ns only, which is twice as fast asthe 74H series. Figure 1 showsa basic NAND gate in Schottky TTL series. Emitter coupled logic (&CL) is faster than TTL family. The transistors of an emitter ‘coupled logic are operated in cut-off or active region, it never goes in saturation and therefore the storage time is eliminated. Emitter coupled logic family is an example of unsaturated logic family. Figure 1.32 shows the circuit of an emitter= ‘coupled logic OR/NOR gate, Veo=45V Fie. 131 Schottky TTLNAND gate | 1.123 Low Power Schottky TTL | ‘The TALS series is low power: iio, btcsa eet Scot assis stor values ale of chasing resistor than reuit power: Voo=-SV Fig. 1.32 Emiter coupled logic OR/NOR gate delay. The 74.8 The circuit consists of diffe ference amplifiers and emitter | i terminals of the two transistors ge d i cle oe Spe ea eee tiene i eli DC level, The circuit has tw Fee ce MLE TE reduce theDigital ectronics__ = Operation ? The input voltage of Tis Vo= Vee ; he input volta in logic 0, 7, and 7% operate in cup tosic0. ie Va, slow, Ts operates in cut-off and Y> is logic 0, voltage Yon and 7, operates in cut-off, voltage Vo, is low, 7; operates in cut-off ang io ishigh, 7, operates in ativeregion and ¥, sj is logic, voltage V, The operation ofthe circuit is summarized in Table 1.8(a), Table 1.8{a) Operation of ECL circuit [Inputs Transistors | Transistors | Oupay>—~ [a eer tats eee Active [Active [Cutoff] Logic Of Loney [toxic o| Logic| cucot] Acuve [Cutt |Cu-otf[Active [Logi Loge Loic Losi 0 Active [Cutt | cutoff [Cu-ott Active [Lope 1) taped [oie 1| active | active [Cutoff [Cucort| active [Loci 4 Lad |teec 0] Logic 0 | Cu-otf|cuo h [tote 1 Interms of and 1, Table L.8@) can be writen asin Table 1.8(6) Table 10) Opeaton of cet Eman | | o O° cease a 4 (OR) i ‘i i a Nor) 1 OC ate iaen I 1 | 0] Fig. 1.33 symbol of OR/INOR gate [ee Jo ut shown in Fig 1.32 acts asa twosinput OR/NOR gate and is uh saa givenin Table 1.8(0). The symbol ofemitter coupled logic OR/NOR gat: is shown in Fig. 1.33, Wired-OR logic Te EL sais wo cup a tt an ase conned ten an atonal loi eli oa alonal hardware. Consider the circuit shown in Fig. is the output of OR logic and Yas A+ B). When the outputs of two ee is realized without Fig. 1.34 Wired-OR logic A¥B+C+D Wa¥+ %=%,+¥ =A+B+O4D Consider another circuit shown in Fig. 1.35 ¥ com nets % Fig. 1.35 Wired-OR logic Y=} +%; =A+B+C4D ¥s=%+¥y=A+B+C+D (sy Unconnected inputs {Tany one ofthe inputs of the ECL gate is open, then the corresponding transistor Gperates in cutoff and there is no current flow through the transistor. The same condition occurs when the inpu ogic O level and hence the unconnected input of ECL is treated as logic 0. ECL characteristicsy fa ——————_—- 5, Fan-outis 25 Logie Families (33) 1.15 INTEGRATED INJECTION LOGIC (Pr 1.15.1 PLinverter Figuee 1.36 shows a simple inverter circuit If the input V, ig transistor T is ff and Jy, =O The input source at 5 sink forthe current supplied bythe em uiput terminals 10% foi Fig. 1.38 /'L inverter circuit with two output ITTENE Soup Pi IND Gate andthe ouputsat high logic evel Ihe inputs high the base cure 1.15.2 PLNAt Ma ss Figure 1.39 shows the FLNAND gate. When inputs A and B are low or any one ASTER 7 aaa egal ottcinputsis ow, tc caren provided by Fssinked the our Ty OF tndinoupatisigh When othe inpusare high te bse caren athe smofcorens provided te sours tnd Fy wast ON an the bape is low v Table 1.9 Truth Table of NOR gate [—Taputs Dusit [-a B ¥ rag 0 1 Fig. 1.36 PL inverter with current source o I 1 7 1 A 1 can Ett 137 shows a simple inverter circuit with transistor 7; as the const 1 1 Mu ‘Simsot source, henee isin series asa constant current source, comma fetes. When both or anyone ofthe inputs is high, the output of the ‘oresponding inverters low and the resulting outputis low, When both inputs are | low, the output of both, the inverters is | high and the result is also high ” Table 1.10 Truth te zi F137 PL overe vas Sl RS _ i with transistor as, ‘Current source z ue the ipso, tp Ass] soa ease 4 7 ‘si stints high teas Cent and Ts and he out re re Ni mu : “ra aly eso ph ; ON oT isthe sum of currents 1; and Osler fe ; 38m ad the ouput is low. 1} xh eal ude ae i Fou other roan pl terminals, Transsi 5 salon i gy 7 : rectly tothe inputs! on Fig. 1.40 PL NOR gateDigital Hlectronics_ Le % 14g MOseeTLOGIC_ 4 ue to their low power dis, 7 ar very popular due 1 nna Fa 105. di) NMOS, and (i) CMOS. ‘three designs Mtl 1.17 NMOS etter Te. aa crelyrdame enccnen MOSER nem SMS 1.17.1 NMOS Inverter Figur 4 shows the circuit of an NMOS inverter consisting ana MOSFETS. When te drain and gate terminals of MOSFETs then tats asa resistor InFig. 141, MOSFET Q, acts as a load resistor switching element. Q; is always ON; the load resist channel MOSFET. Instead ofload resistance, Q, isu the chip. Q; may be of depletion type or enhancer. ‘enhancement type Operation * When the input si Te shore ind MOSREr gyal ance is equal to Roy ofa ed, which reduces en pe. But Qs sat =a ; ignal is high (positive (J, posse), Osis ON, the current flows through Lo re, | * When the input signals low (OV or negat ornegative Yollage), Q3 is OFF, there is no current flow (qoweh the circuit and the output is high ie op). The operation ofthe bg jcuitissummarized in Table Fig. 1.41 NMOS invete nate of 0 and 2, we ean wees Table 1.11(b). The circuit in Fj 3. 1.41 ik Bivenin Tale Liga nA acts as a NOT gare and its rth a Table 1.11 @) Operation of NMOS inverter leh Table 1.11 (b) Operation of NMOS inverter Raa Logic Families 95 sre molled by thet and BO ny be of depletion ype orenkancement Pe, put Qz and Qs are always en! oe 3 ih po! «When sry ons of tho inputs Jaw (OV ‘or negative), then the corresponding «When inpus ae high ve voltage), Qs and Qs a6 ON. The eu rood otra al ad ae cena Fig. 1.42 A two-input NAND fate using NMOS The operation ofthe circuit is summarized in Table 1.12(a). Table 1.12(@) Operation of NMOS NAND gate a ae ee se A Low | tow | OFF | OFF | HIGH tow | HIGH | orF | on | HIGH uch | Low | on | oFF | HIGH nich | mcH | on | on | Low In terms of O and 1, Table 1.12(a) can be written as in Table 1.12(b), Table 1.12(b) Operation of NMOS NAND gate A B Vo 0 0 1 0 1 1 1 0 1 1 i 0 ‘The circutshown in Fig 1.42 acts as two-input NAND gate and ts truth table is given in Table 1.12) 1.17.3. NMOS NOR Gate Figure 1.43 shows a two-input NMOS gate, Qj acts as a toad resistor. Itis always, ON. MOSFETs @> and Qs ae the switching elements, These swit are connected in parallel, which ar controlled by inputs A and B. Insta nd prone sel which rece the sizeof the chip. Qy my be of depletion Rea aera mene Aa " AUT © 2 a NY aoa pea aROperation < ~ When bath he inputs te low, Qs and 2, are OFF. The though the drain terminal andthe ouput is high Vee cag fh * When any one of the inputs is high (0 v . or —Ve), then th MOSFET is ON, The current flows through the cireuhe One, Circuit and the og Py ut * When inputs are high (#ve voltage), Qs and Qsane nt through the drain terminal and the output is iow." ON’ THE curen, Tre operation ofthe circuits summarized in Table 1.13¢, Table 1.13(a) NMOS NOR gate ASE See Low | Low | org | OFF Low | iicH | or | on HIGH} Low | on | op: mic] mc | on | on In terms of 0 and 1, Table 1.13(a) can be wr ritten as in Table 1.13(, Table 1.13(6) NMOS NOR gate ees Sorcha, a B ioe 0 0 1 0 1 0 1 0 0 t 1 1 0 } The circuit shown in Fig, 1 -43 acts as a two-inputs NAND gate and its truth table is given in Table 1.13(b), Yon 2 % oe ah el Fig. 1.43 NMOS NOR ‘gate 1.17.4 Fan-out Logic Families 137) 1.17.5 Propagation Delay Time : oe Itisa function ofthe capacitor of fed ata te carsing esi I of MOS devices, C capacitor is presenta input and output an the resistor togh whic he capctr gets charged or icharge ils igh Hence rropagaton dely is fargeand the sped of operation is 1. 1.17.6 Power Dissipation ae jncton of caren supply bythe sours and resistance fhe loud, The power aipoly bythe source in MOS osc familys smal nd hence the power disp 1.17.7 Characteristics of NMOS Table 1.14 summarizes the characteristics of NMOS. Table 1.14 Characteristics of NMOS Parameter | Value | Parameter | Value | Parameter | Value Ya | 20. ey 400 WA, Tal 60 ns. yy | osv ce. 2mA ne 45 ns Vox =| 24V | Fan-out 20 PD. 1 mw Vo. _[.0.45-V | Noise margin | 1.5 V 1.18 CMOS (CMOS family uses n-channel andp-channel MOSFETs. In CMOS, p-channel and ‘channel MOS devices are fabricated on the same chip, which makes its fabrication ‘complicated butt reduces the packaging density, and has small power consumption, Hence, CMOS is ideally suited for battery-operated systems. 1.18.1 CMOS Inverter Figure 1.44 shows a CMOS logic inverter, For the circuit, the logic levels are 0 V and Voc. Itis RS important to note that the p-channel MOSFET. a Dy is ON, when the input is 0 V and the n-channel 1 in MOSFET is ON, when the input is Voc. Q, is p- Eas channeland Qzisn-channel, When Q,isON,the 4 —_| o ‘output voltage is equal to Veg and when Q5 is ON, the output voltage is equal to 0V. Frere, ee fea 1 Operation rs * When the inputis tow, is ON and Q, is ; + OFF, output is high, Lhe * When the inputishigh,Q;isOFFandQ, "#8 144 CMOS invert is ON, output is tow. ,38 Dioital ectronics Table 1.15 shows the operation of CMOS inverter. 4 Table 1.15 Operation of CMOS inverter 1.18.2 CMOS NAND Gate Figure 1.45 shows a two-inputs CMOS logic NAND channel and two n-channel M Parallel and n-channel MOS} ‘channel Mos Fig. 145 CMOS NAND gate Operation * When the inputs are low, Q; and Q, are ON, Q3 and Q, are OFF, and the output is high (Vpp), * When any one ofthe inputs is low (OV or ve), then the corresponding MOSFET Q, or Q2is ON, Q;0F Qs ON, and the output is high, * When the inputs are high (+ve voltage), Q, and Q, are OFF, Qyand Q,are ON, and the output is low. ‘The operation ofthe circuit is summarized in Table 1.16, Table 1.16 Operations of CMOS NAND gate aEEaSSSsSsc_xcxc“™“ i} OS NOR Gate sists of wo p-channel is au 1o-inputs CMOS log NOR Bat rae and Ee SSR ma ose ommestedinllng ind two n-channel en Here, Q; and Q2 * connected in series. is low, p> sine ee pies die e a a Noster aes Ya Le Oe METS OPE high, p-channel is OFF and n-channel is ON. Wee 9%, o Fig. 146 CMOS NOR gate Operation * When inputs are low, Q, and Q, are ON, Q3 and Q, are OFF, and the output ishigh (Vpp). * When any one of the inputs is low (0 V or ~ve), then the corresponding MOSFET Q, or Q3is ON, Qs or Quis ON, and the outputs low. * When inputs are high C+ve voltage), Q, and Qs are OFF, Q, and Q, are ON, and the output is low. Table 1.17 Operations of CMOS NOR gate 22 oS Tan ae 1.18.4 Characteristics of CMOS ‘The S4CI74C seties isthe c characteristies of S4C/74C CMOS i il ven it L ee ogic family are given in Table 1.18 fora supplyWO Digital Electronics Table 1.18. Electrical characteristics of SAC/7AC CMOS logic fy Parameter | Value | Parameter | Value a Von 35V) Tn ThA joa 13 he “1A 100 pA | Ye 45V fe ¥ 7 osv | & 360 yA (ana Operation speed of a logic family is defined i terms ofits propagation delay 1, The spes propagation delay, fu. * fou 2 60ns +45 ns 2.5 ns Noise margin Itis the capability ofa gate to tolerate noise. Logic | level noise margin = Von — Vins 5V-35V=1V al Logic 0 level noise margin = Vj, = Voy. 40=15V-05V=1V Farrout MOS devices have a very high input impedance; therefore, the fan-out is large Fan-out of a CMOS is 50 for low frequency and less than 50 for high frequency | inputs | erate | Itisa function of current supply by the source. The current drawn from the supply _ in CMOS logicisless, Hence the power consumption in MOS circuitis ess. over dissipation for CMOS logic family is 1 mW at 1 MHz. Itis less than 1 mW for frequencies less than 1 MHz. Unused inputs ‘The IC of a logic family may have more than one gate. CMOS inputs have tobe Connected with a fixed voltage level orto another input. If inputs of unused CMOS ules are open, they are susceptible to noise and static charge that could bias both and n-channel MOSFETs in the conductive state and power dissipation is increased: 1.18.5 Buffered and Unbuffered Gates (CMOS circuits are available intwo vers thbufferedou! 204(6) CMOS wit nbd oe ey OMOS wi We have discussed unbuffered, : ora eanive discussed unbuffered outputs of CMOS inverter, CMOS NAND gat: togic Families ati) cea te is increased and it reduces the speed the output, the propagation delay oft of operation |.18.6 Transmission Gates : NMOS, Gues of ©} and Qs are controlled by the controled inputs C and C, Repastely = Whenc=1 (igh), Q\and Que ONor OFF depeing uponthe input When iyta hgh the 0 BOPP incoming he ohmireien: bees and output ¥ asa small resistance connecting the output tothe inputand output a input Ais low, then Q; is OFF and Qs is conducting in the ohmic region; Q2 beha as.asmall sistance connecting the output ote input and output ¥=A =1ow ‘When C=0 (low), both the MOSFETs are OFF and transmission isnot possible. In hort a transmission gate isa digital controlled CMOS switch. The symbol of transmission gate is shown in Fig. 1.48. 4| Control 2 = apt | Out " on |r } m Fics 2, seu ptas 2 Fig. 1.48 The symbol of Fig. 1.47 Circuit of transmission gate transmission gate 1.18.7 Open Drain Outputs Different outputs are available in CMOS logic family asin the TTL family wehad Aiscussed earlier. InCMOS, opendrain outpatis possible by replacing the transistor with a diode. See Fig. 1.49, Yoo op et Rex [| ro, a joa : 4 Fa L | 2 Ir pac ¥ ¥ Fig. 1.49 Open drain outputs ata ede protection rom electrostatic discharge, A in TTL, an ‘external pull-up resistor is required to take the output. Then nen tees aDigital Electronics rosie Families 49 1.18.8 High Impedance Outputs ee ‘output CMOS logic family issimilarto the restate Ves he high impedance i Saad Thehigh ime eh ahows the hgh impedance oIput CMOS nga | 1.19 COMPARISON OF ¢ Sane To ee ascnclw np Whos Eslow.0;wilteONSSEH | TpgcMOS and TT amis compasdam togrictts and (epa low. Now athesane tine, Qs so Thos iS snus high When he enable ip sow and he input ihigh, yj oS 4.20 Comparizon of CMOS and TTL fails inpsto and Qs respectively, re high. So O; willbe OFF and Qs wi ye! sa —_ " me ‘Sili m4 7a. | 74AS | 74ALS Ena eB ietaee gees Sila OS Saad ~ v Zov | 20v | 20v | 20V aa Laren ae aay fosy | osy | osv Id cate 49V 2av |27v[27V | 27V eee olVv o4v [osv | osv | 04V o Header 5 dav forv|oav [ory os vee 09V oav jo3v | 03v | 04Vv in Sins ios | 1 | 15m | 4m raw | tan BT Ib. cer gu)] 017 mW ome | 2mW [as fete | cise | tose) | sors | 2003 [12g | 4s Fig. 1.50. High impedance output CMOS logic family ae en c-fos ny eabseond and With Wa When the enable input is high, E+ is always high, and E/ is always loy “The fan-out of CMOS is more than TTL. Itis typically 50 for CMOS and 10 for independent of input high. Due to this, Q, and Q; are OFF, and the output is ing ‘TTL. CMOS is more susceptible to noise than TTL. high impedance state. 1.20 INTERFACING CMOS AND TTL DEVICES 1.18.9 Specifications and Standards I Interfacing means connecting two different systems or devices, having different ‘The ELA [Electronic Industries Association] has established certain standard gait electrical characteristics. Insuch case, direct connection isnot possible. The circuit stecicaons for MOS circus. In standards to differentiate buffered CMOS. B Gediocomocceveranl lacie tetsu alist a tein tacos rete ee ified as B-types and unbuffered are identified as VB types, circuit takes the input from the driver and converts it, so that itis compatible with the requirements of the load Following are the important factors to be considered: * The driver output must satisfy the voltage and current requirements of the Table 1.19. Electrical characteristics (Supply voltage Voo = 5 V) Value Toad circuit. a5 * Thedriver and load circuit may require different power supplies. In such cases, aN ‘he outputof both circuits must swing between their specified voltage ranges, 45v 1.20.1 TTL Driving CMOS, OSV in E As TTL is driving CMOS, it must meet the current and irements re the load device. Supply voltage is 5 V. taps i -1pa. 100 uA Table 1.21, Current and voltage requirements of CMOS and TTL 360 pA cmos 2 60ns ; 45ns 1omwIogie Families CAB ‘The above discussion of CMOS and'TTL interfacing is only for standard CMOS and standard TTL logic families. For other families, like high speed, low power, itisncoessary to compare the output capabilities of driver and the input requirements of load on the same lines as above. 1.21 INTERFACING ECL AND TTL DEVICES pigital Blectonics_ le ierei a Jorn te TLtasno oben diveth Chg, From Tube 12h pent of CMOSIS Very OW a COPS an he inpacurenreqiem capatliies of TL fa —+—“J [gies san AP SE Mos Fig. 151 TIL driving CMOS TL 1.20.2 CMOS Driving iisneesary wcheck he CMOS ouputcapacityandthe TTL inputrequiremeny, Table 1.22compars thet. Table 1.22 GMOS output capacity and TTL input requirements ‘EMO (4000 B) TTL Vi (nin) = 495.0 Via (in=20V | (max) = 005 Y (max) | Joy (ie) =04 mA, di (ni gx) = 0.4 0A 4 (max) = | HA microampere and mA ~ miliampere From ibe stove tabi is rved ta the CMOS driving a TTL inthe high state donot nee any special consideration such as, Vow (CMOS) > Vi (TTL) ou (CMOS) > Fy (TTL) Forthe CMOS diving a TTL in Jow state, see the parameter Voy (max) CMOS < Vy, (max) TTL Thissatisies th requrementin the ow state. Now se the curent parameter, iSO ee ; [> fo, (CMOS) < hy (max) Se Buffer meres) es ot satisfy. the TT tapas FUSE CMOS driving TTL Interfacing means connecting two different systems or devices, having different clectrical characteristics. Insuch acase, direct connectionisnot possible, The ci used to connect driverand load circuits called asthe interface circuit. The interface Yo, (TTL) YulECL) > Voy. Translator),[shows that the input logic le logic levels ofa TTL a Vels of, at and the output logic, com, = the input logic levels of we Hevels oF arama ti wiclevelsof an ECL. Fipare "anlar ape Bate. ig 154 Shows they egy, Fig. 1.5 1.21.2 ECL Driving TTL An ECL cannot interface directly with a TTL; it requires a translator. ‘The MCIOH125 is an ECL to TTL translator. The logic diagram of MCIOH124is shown in Fig. 1.55; it isa 16-pin IC and ituses two power supplies. The logic levels of the translator are: =-113V, Vy =-148v, 2.5 V, and Vo, =0.5V Ishows thatthe input logic levels of a translator are compatible with the output logic levels of ECL and the Output logic levels of a translator are compatible with the input logic levels of a TTL, Figure 1.56 shows the ECL gate driving a TTL gate. Til eke ro. pe a anion Sig 54 TTL driving ec (e031) ety xp : Fig. 1.55 Logic diagram of MC Logic Famities (th \ARY TT ges —— sum a ofthe following advan erated iit because ofthe olowing adenine: ten digi systems vse inex ss toa of Scan of dig sytem gets eed, Ds of digital ees 2.The cost of 5: mer comune They have high noise margin They have igh relay. 6. The operating speed is high oe «The foie families ate classified ino two 1 6) Unipolar logic families. cet «pur op faites re fr li oS ta) Und ptr aie asia oi, * Br SRNP Satan amir lope) negated injection fog, Diode: (Diet coupe rani oi, nea injection owe, Di transistor logic, (e) High threshold logic, a ete Pe fd bipolar logic families are: (a) Schottky transistor logic, and (b) Emiter- coupled log «ieee se 8, SNOB, CMOS + The various pramates of itl ICs used to compare their perfomance ae (sero orton, Power dat, 0 geo ent Fe (©) Fain, © Current and voltage parameters, (g) Noise immunity, supply requirements, and (i) Operating temperature. ee BY recom pr (lat Drees ae of operation is low (12 ns), and (8) High power dissipation (typically 12 mW). ‘+ The DCTL is simple than RTL, itis not popular because of the current hogging problem. standar Lup, (b) TEL with + A standard TTL. canbe classified as; () TTL with passive pul-op, (6) ‘otem-pole output (©) TTL with open collector output, and (d) Tri-state TTL. very Tow (@) Bipolar logic families, and rated bipolar logic families, jum KEY TERMS AND DEFINITIONS == Integrated circuit Most ofthe digital circuits are constructed on @ single chip, ‘hich ar refered to as integrated circuits (IC). ‘Logie family The set of compatible ICs with the same logic levels and same supply ‘oltages, fabricated to perform various logic functions, are known as logic family, Unipolar logle family “The logic family having unipolar devices like MOSFETs 45 its key clement is referred to as unipolar logic family. ‘Bipolar logic family “The logic family with transistors and diodes a its key element is refered to as bipolar logic family. Resistortransistor logic (RTL) ‘The logic family that consists of resistors and ‘ransistrs is called as resistor-iransstor loge, ‘Direct basil Gea a) La DansPiode-tranistorlgle (OTL) The logic tamiy With dio s diode as its basic element, which Operates eithes re family ee Integrated injection logic (PL) Tt uses nly transistors for MOSFET logle MOSFETs are vecy popular for logic crn on Power dissipation and high density of fabrication, cathe cng, ante case e uN EXERCISES Review Questions og singles th stag tf 3. Explain the tote, fora TH fora TTL gate * NaND gta das, capa ewan fy, NAND gate. What is the advantage of active load? a eel Dg parameters of digital IC files an gn values for TTL and CMOS families, % a @) Propagation delay (©) Fan-out their ypc () Noise margin @ Figure of merit 7- Explain the following parameters: © Propagation delay (©) Noise margin eit short note on CMOS loge family Tie fetes dele inorored neem poe TL ogc? sis of be following pramctrs for TTL snd CMOS le wes a ae ___ @) Power dissipation ie eel Nie omer sate (@) Power dissipation val nai ti re ‘L NAND gate with a neat diagram. Explain the pepe erinret (©) Totm-poe up (© Tite ona erect Exp tc bcc ECL OR/NOR gue wih not ie cng a ECL family have the lowest propagation delay of all logic pues Give typical values of the following parameters for CMOS logic 2) Heneaegaa () Fan-on : ‘hss en ty asia a yg ee ate ek ate driving CMOS gates and vice vers 16, Explain interfacing of a TTL gate driving aioe 17, Define the following parameters of logic families and give their typical val fora standard TTL pate (©) Propagation detay (6) Fanout (©) Nolte arya {0 ome Exphin witha net cic gram the t-te TTL gate How can the t-te Sita up conned ogee to orm eae a a ek an an be teed om he bun wie? 19, Draw neat circuit diagrams of: @) Two-inputs TTL NAND gate with totem-pole output (©) Two-inputs CMOS NAND gate Multiple Choice Questions Select the correct option. |. Positive logic in a logic circuit is one in which. respectively. () logic 0 voltage level is (9 Totie 0 and I are represented by negative and. poaldve voltagesetn * ¥ re of merit of a logic family is given by Se ‘bandwidth product , e ae ation delay time and power dissipation Ort of one : oise margin and power dissipation (ay produc of nose mare Which of he following uses the least power rm () ECL (9 eMos (€) all use same power Which of the following logics is the fastest @ ™. @) ECL (@ cmos hore {In Schotty-clamped TTL, the purpose of Schottky diode is, (a) to increase propagation delay (b) to achieve efficient non-saturated switching (©) toimprove noise margin @) 10 decrease dissipation Pe ee es { .@ 20) 2 © < Te aa Numser SysTEM AND CODES Chapter Outline + Number systems and thelr interconversion + Sign binary numbers + Binary arithmetic +2 complement arithmetic + BCD code and its arthmotie + Ex0265-3 code and its arithmetic * Gray code «+ Party code, ln lock code, and hamming code 2.1 INTRODUCTION Incase of digital systems, datais represented by the binary digits Oand 1 which are known as bits. A group of eight bts is known as byte and a group of four bits is ‘known as nibble. In digital systems, the information is represented, stored and {ransmitted asa group of bits, Thi group of bits is known as binary code. In othet ‘yaaa the binary code isa binary representation of numbers, alphabets, special ‘This chapter includes the study of different codesber he na aseoft stem adixorbase tm he integer p ner of gis 1h oo jn fractional part 45.7 most significant digit (sb) jest significant digit (sb) i + ofsymbols and radix, number systems are 7 laf of umber nthe bass of ary mune sytem (i) octal umf oy OS aterm 221 Decimal Number System ‘ints ptonn umber Thetis. igthas the mexmaa 8 a ea agi SD) Te a For example (55538).g= 5x10? +5% 10!+5% 10°45 x 10-4592 2.2.2 Binary Number System Inthe inary number system, the total numberof symbols are two (0, 1) bai andthe ax point is known she binary point. These symbols are knowns (binary igits)tisa positional aumbersystem; the weight of abit defined Postion with base 2 For example, (LIM), = 1x24 1x 2 41x 2! 4124 1a $1274 1x2? I 2.2.3 Hexadecimal Number System system and Codes 153 Inthe hexadecimal number system, the radix point is known asthe hexadecimal point. lisa positional number system: the weigh of adigitis defined by itsposition With base 16. 2x 16+ 1x 16 + 5x 16! + 10 x 16° $216" 46% 167 48% 16" For example, (215A.268),6 This number system is used to pass the data to the computer system by using 16 keys. Itis the most commonly used number system in a microprocessor kit. The keyboard ofthe microprocessor kit is known as the HEX keyboard 2.2.4 Octal Number System. ‘The number system with base 8 is known asthe octal number system. Eight symbols are used to represent numbers in this system, and these are: 0, 1;2,3, 4,5, 6, and 7. In the octal number system, the radix point is known as the octal point. Itisalsoa positional number system; the weight ofa digits defined by its position with base 8, For example, (576.217)_=5%8?+7%8! 46x84 2x8" 41x8247 x89 2.3 INTERCONVERSION OF NUMBERS {Computer systems process binary data. The information given by the user may be in the form of decimal number, hexadecimal number, or octal number, So an Understanding ofthe system operation requires the ability to convert the numbers from one number system to another, c fe binary nun ‘onsider the binary number: @cBsBrB\By-B)B2Ba), (2.2) “The frst left bit from the binary points denoted by B, i Decimal eguivalent of (2,858, By «BB 4 2! Bcd ep, x aie +Bax2 eB x23 PB aT a Ry 294 ny see F1X2 40x22 412! =16+8+2+1= 027), rita4 1x2240x27 + 124 ji) (0.1101): = 1x2" + 1X? 1 yt yo+4 2*4° 716 =05 40.25 + 0.0625 (08125)0 x241x240x2 41x20 +0> =8444041405 +0125 +0+0.0605 = (138125) (1101.1101)2 = +1 xaty Gi einai wy 2.3.2 Decimal to Binary Conversion ‘Thereare two methods toconvert decimal number to its equivalent method. i Sum of power method Inthe sum of power method, the decimal number is ex} of 2and then Is and 0s are written in the appropriat opposite of binary to decimal conversion. Pressed as a sum of poy, te bit positions. Ibis jut, 1010), Gi) yo =16+ 8404241 SIXD4 1x2 40x24 1x2! 41x20 = (11010), (il) (075), S1x2441 x22 =D; (®) 21.625) = 6+0+4+041405+40+0,125 XM 40x 341 x 92 1 01 yo Boies +0x241x241 = (10101.101), This method ig sum of maga }Y used, as itneeds the number to be represented but itis dittean est © 8 Power of 2 form, I, bbe easy for a few numbers, ficult for may be easy ies ee aa eA | | | umber System and Codes 551 Repeated division and multiplication method nteper and fractional parts ofa decimal number: are treated separately for the oa integer part of decimal version. The repel vison methods sed forthe integer art of evi ‘hombers andthe repetitive multiplication method is used for the fractional part of decimal numbers 2) Repeated division or integer decimal number) ; * nhe repeated division method, the decimal umber divided by 2and the reminders found afer each vision antl he quotient 05 obtained. Note thatthe inary ess obtained by waiting the rt emainder a the least significant bit and the last remainder as the most significant bit. For example, (25)\0 = (2). Quotient Remainder aseore 12) 1 +LsB 1222 6 0 622 3 0 oa 1 1 ee 0 1 oMSB Ans: (25)0= (110012 Repeated multiplication (for fractional decimal number) Inthe repeated multiplication method, the fractional part of the decimal number is mokipied by 2; the integer part of the multiplication is found afer each multiplication operation, until the fractional part of a decimal number becomes ero, The fractional part of the binary result is obtained by writing the frst bit asthe MSB and the last bit asthe LSB. For example, (0.625) = (2), b) Multiplication Integer part 0.625 x2= 1.25 1 «MsB 025 x2=0.5 0 05x2=1.0 1 + LSB Ans: (0,625)10 = (0.101), Now, letus consider decimal number that includes both an integer part as well ‘sa fractional part. Such a decimal number is converted to its binary enuvaleanby ‘epresentation ofthe integer decimal number and the fractional decimal number For example, consider (57.825)jo. The integer part of this dec is $57 and the fractional partis 0.825, eee Conversion of integer part: Quotient Remainder e 1 + LSB 4 0 a 0 3 1 oe { Gansaniee ae se 1 oMsBy ee : NEED somal pa Conversion offre Imegerpart ttiplication poet ee i ‘The integer part ofthe given decimal number is 79 0 Quotient Remainder B+ 20ha aD: 1 + Lsp ae ete 34219 1 (0.825)10' fhe Zs 7 rs (57825)p= (111001), + (041012 = (11001. 1101, 942 4 1 PEAS o ranplo 21 Coavetefoing inary numbers their decimal equi Ceara oa 0 (@ 10010111 (b) 10111.0110 © wut ee i Mi 1); Solution : eo ati rere eee re ‘The fractional part ofthe given decimal number is 0.515. ne Ixp Mutiplicasion Inceger part 28 + 16444241 0.515 2 = 1.030 1 oMsB rane 0.03 x2 = 0.060 0 vate gente i 0.06 «2 = 0.12 ° ) avast gl le +1xP41x2! pletion al 0.12x2=0.24 ° mae 0.242 =048 ° s16+442414 245 | 0.48 x2=0.96 0 = (233750 0.962 = 1.96 1 oLsp : E (0.515)i9= (0.100001). se © MOUNTS Le O21 1ee8 1oc?? ater a Ans: 79.515) iy ©) (109.125), ates - sersesone ded ‘The integer part ofthe given decimal number is 109, = (47.75)i0 Example 22 Convertthe following decimal Pe ©) 9 vn MERU Ce ae ) rab (©) (109,125),9 SolutionJ ga 3.33 Octal to sion imal Conver a fi soa psitoral number), Wen each og 4 iersystemis ali its position relative to the octal point That rain welt bed Oe guvalentby summing the weight f= canbe forthe conversion ofan octal number to it oe deci rhe octal nu razed method fort ained below ihe octal umber: 0,040:0109 + 0.10.20. Consider the octal points denoted by Oo. Subscript 0 de tnt eccrine Op Steet a tons. ee ent sex uk gui Fines thy Value pa en noone 00 a The dial aber fhe cal number psc ST aeuRORE a0, SOA a snl 40..x87+05x8 cae : i) (7539 7x 82+5x8!43x8' sae aie (ii) (0.235), =2x8143x8245x8> 25+ 0.0468 + 0.00976 (0,30668)0 (ii) 265.731)y =2x8°+6x8! 458947 x84 43x82 41x89 = 128 +48 +5 +0.875 +0.0458 +.0.00195 = (181.92375)i0, 2.3.4 Decimal to Octal Conversion Theintger and fractional parts ofa decimal number are treated separately forth conversion (a) Integer number The integer part of a decimal ‘fumber can be converted to octal by using the repeated division method. The integer part of the decimal number s divided by 8, and the femainder is found after each division until the {Quotient becomes zero, The octal number is obtained by writing the firt remainder as the LSD and the last remainder as the MSD. For example, (266),9= (7), Number System and Codes 59 (0) rsetonal number ; ato pa of cia antec obra oi ca valent using the repeated miplcaton method. The rational part of the uecimal number i muliptied by 8, and the integer prt afer each Imuliplieation operation i found unt the fractional prt Of the decimal number becomes vero. The atonal part ofthe otal rest isabtained by ‘rng the fist nteger asthe MSD and the last integer a the LSD. Fer example: (0250) Multiplication Integerpart 0.256 x8 =2.048 2. #MsD 0.048 x8 = 0.384 ° 0.384 x8 = 3.072 3 0.0728 =0.576 0 0.5768 = 4,608, 4 *LsD Ans: (0.256)y0 = (0.20304), The decimal number that includes an integer part as well a a fractional partis converted to the octal number by using separate treatments over the integer part and the fractional part of the decimal number. The octal representation of such a scel HMieaGees 7 oa (125)o=(D)ig | Conversion offracionalpat I he | Seen Sig ata ts An Sa oat6aig pase a if 4 i B @LsD D)is + (0.33748), = (7.33748), 23 i " a4 Hexadecimal to Binary Conversion A hexaiecina muni ofa 'salsoknownas.a4-iti 3 Table 23, "ambercan be; inary number, because eae! by a4-bit binary number, as ve" [ Weradecimat Binary Hexadecimal Binary (aa of ; ie cag cl A io 3 oon B roi | 7 oul uit | Theconversionofeachhexadecimal dgitoits 4-bit binary equivalent performs the conversion from hexadecimal o binary. () G7A)= Qe 4=0100, 720111, A=1010 Ans: (47A)\g= (0100011 11010), Gi) 0269)6= Or 0010, 6=0110, 5=0101 Ans: (0.265),s = (0,001001100101). (iil) F23.6A1)¢= F=1111, 2=0010, 320011, 6=0110, A=1010, ‘Ans: (F23.6A1)6 = (111100100011.011010100001). 0001 2.3.10 Binary to Hexadecimal Conversion ‘hate at different methods to conver the integer and decimal pats of binary hhumnber into its hexadecimal equivalent (a) Integer part cauivalent by making groups of four bits starting from LSB and moving ‘owards MSB and then replacing e, hexadecimal representation. If ach group of four bits by its equivalent thenumberof bits is less than fourin the last For example, (100011110101), = 1000 1111 o101 SF5);6 (b) Fractional part ‘Sr0up, add zeros to the right side, For example, (0010111101), = 0.0101 1110 1000, i a aetectroi a a rumberbaing both inte and fixcy. it : 3 sort mp 010101 = er part = 101001011 pes F100 = 0010 1001 0111 = 097 01 «ional part = 0.01101 - 0.0110 101 0110 1010 =(06A)g 1010010111,0110101 = (297)¢+ (0.6A)is = 297.6A)ig fhample 27. Conver ie following decimal numbers to thei Hexad egoivalets: (by adding 100s tothe egy (by adding one 010 the righ @ 2)» (©) (03560 © 214356, Solution ( @14) | @ 29 4 Decimal Hex | me 4 6 6 +Lsp 13416 a) Msp Ans: 218)9= D8ig (0) (0356) umber System and Codes 67. Solatton (a) B56) x16? +5 x 16! +6 x 16° 3x256+5%16+6%1 768 +80+6 = (65t)0 (b) 0.21) =2% 16+ 1 x 16 es 16 * 356 =0.125-+0.0039 = (012899 © @AF3Dy X16?+ 10% 16! + 15x 1643 x 1644 1x16? 256+ 10x 16+ 15 +316 1256 =512+ 160+ 15 +0,1875 40.0339 = (687.19},0 Example 2.9 Convert the following binary numbers to their hexadecimal ‘equivalents: (@) 1010110110111 (©) 101011011001.1010100 Solution (@) 010110110111) = 1 0101 1011 O11) =0001 0101 10110111 (by adding three Qs to the left) =(1SB7)i6 el (b) (0.010011011).=0.0100 11011 (b) O.01001101124 SI wor negative signs ar know ened ng re uber who PO ays considered a8 Positive numbers, typ ‘omigmt abe a2 Pen or meas Ihe de BS essen a nebo th umber o define Pog a) se peat ee e berta lefine anegative nyt co ine BY a pers negative and when ij! ee oe epee NE the number is neg tisq ste ub sin ti Men menisci enone eeentatn 2 sods sed to represent sign binary numbers, + 2'scomplement p tation 1-Magnitude Representa by oe resentation of abinary number, the MSB represents aor ruinng bs eresent its magnitude. When the MSB is 1, the and the reninng bits represen negative; and when its, the signi positive Consider te binary number: (BB BB BBB By where By represent the ign and Bt By represent the magnitude of the bing umber. Forexample: 00001000 48 0091000 8 oun #127 mn 127 bedi sig ‘The unsigned hi binay representation can represent the maximum deta Wet the pstve number using Pits Step 4: Find the decimal equivalent. —_ 7 (460 = (010000002 MOOLI1= 1x 284 1x 28-+0x2440 x24 12? + 1x2! + 1X2 rhe sconpinetepresntatin ofa postivenamber Same ase 264432444261 ‘ie representation ofa positive m ie Fenn scomplement representation of (+ 649 = 01000000 Hence, the decimal equivalent of (1001 1001);=(-103),0 e number. ‘ 2 «)_ Sep | Fine binary equivalent of the m (b) Given number is (01100111). anil Quotient Remainder ‘Step 1: Check the sign of the given number. 22M 1 +1sB “The mos significant bit ofthe given number is O, the sign of the number is : positive ee aeate v Step 2: Since the number is positive, goto step 3. ee ee e Step 3: Since the number is positive, go to step 4. Me? 5 1 Step 4: Find the decimal equivalent. Sates i MOOI =1x26+ 128 +0%24 +0241 x24 1x2! +12 at ont p =68432444241 eer 1 +MSB 2103 Hence, (89)p= (1011001) Hence, the decimal equivalent of (01100111) = (+103)jo Caan earns) 10 te tel) (©) Step 1: Check the sign of the given number. ‘Step 2: Write the positive number using 8-bits. ‘The most significant bitof the given number is 1; the sign of the number is (+89}o= (01011001), negative. ‘Step 3: Find the 1's complement by replacing 0 by 1 and 1 by 0. Step 2: Find the 1's complement of the number. 1’s complement of (10101011); = 01010100, 1's complement of (+89) o = (-89)io = (10100110)2 Step 4: Find the 2's complement by adding 1 to 1’s complement. 7's complement of (+-89),9=(-89)jg= 10100110 Step 3: Find the 2’s complement of the number. 01010100 a 1 * 1 oa 010 01010101 10100111 cit : ‘Step 4: Find the decimal equivalent. Hees hes complement representation of (= 89)q = 10100111 1010101 = 1x 2°+0x25+1x 2440x241 x240x2! + 1x2? Example 2.16 @ (10101011): oi Serenata ile =85, é, * Hence, the decimal equivalent of (10101011).=(85)jg Piet: | see | Find decimal equivalent ofthe following binary numbes 2644164441 itp ertints H oea pot REPRESENTATION. OF NuMBER sn a imran 709.739is represented in scientif 1729.739is rept titi notin, be afied pint faction Mis tepresengig | compen a afrction 10 times By an exponen iseauvale sap exressed bythe sciente NtaiON no | the! hating Pn spats: the first part represents & signed, fixed point nuts set a tat oon catia a The eatng pint numbers represented (ayx Sinica) xP = 26 ste sin bit defined as s=Oforpostive numbers and s= 1 fornegat ae ert a a conto the ange ofthe number. These mantissa and bias exponent ax ‘Rpesetedy th number ofbitsinbinary. Thenumber ofits is used to deter ‘roscsuracy ofthe stem. IEEE has defined two floating point standards alk assingle precision and double precision. ; In single precision, the word size of the floating point number is 32-bit ani 127 isthe bis, The format of single precision floating point number is showni Fig, 21. Outof these 32-bits, MSB (Ds,)is used for sign, LSB 23-bits (Dz1oD) are used fo significant and 8-bits (D3pt0 Dax) are used for bias exponent. sidered ere the mantisssconsidee tt the nu ary by the expression Du Dp Dn Dm Do 3 [Basen | Scar] Fig. 2.1. Format of single precision floating point number Let us consider the example of a decimal number 44.25. Its bin! representationis Number System and Codes (7 ‘Significant = 10110001000000000000000 the sum of exponent value (5) and bias (127). Itis given as feaeres Blas exponent 5 +127 (1320 sng be converion techniques. itsbinny representation lias exponent = 10000100 ‘he mnheris poste, ene the sigaits 0, and he sngle precision oating pola appeceaa fe pressntet ie [0 [10000100 [_1011000;000000000000000 tn double precision, the word wz ofthe lating pont numbers 4-bits and asestbe bin, Te fmt of double precision floating pont numbers shown in Fig 22 Ouot hese Ohi, MSB (Dy sued fr sign, LSB 52-is Ds 10 Do) Sind for significant and IIs (Deto Dy) ate used for bias exponent. Das Da Ds Psy Do nas [Bias exp Fig. 2.2 Format of double precision floating point number Let us consider the example of a decimal number 144.125. Its binary representations (144.125),9 = 10010000.001 0010000001 x 2” ‘The mantissa is converted to 52-bits significant value by putting zeros to the right side of the number as ‘Significant = 1001000000 100000000000000000000000000000000000000000 ‘The bias exponent is the sum of exponent value 7 and bias 256. Itis given as Bias exponent =5 +256 = (261)yo Using the conversion techniques, its I1-bits binary representation is Bias exponent = 00100000111 ‘The number is negaitive, hence the sign bitis 1, and the double precisic floating. Point representation of the given numberis: Sera {901000001 11] 1001000000100000000000000000000000000000000000000000) 2.6 BINARY ARITHMETIC ‘The computer is a digital system that supports various arithmetic operations. Performs addition, subtraction, multiplication, ietayschyoe denna! learn the basic circuits of a digital system, it is necessary to study binary‘multiplication, and binary division. 2.6.1 Binary Addition “The addition of two binary numbers is performed exactly inthe same aoe toate On oressccrin tendon St bis 000, d=}, 140=1, and 141210458 hsm = anda, ‘The rules of binary addition are given in Table 2.4 Table 2.4 Sum of Binary bits A |B | Sum | Carry o fo] o 0 ° 1 1 o 1 ° 1 0 1 1 o 1 ‘When the binary number re more than one bit the addition takes pace ity bit, which starts from left side. The cary of the previous sum is added to the ny bit addition. : 10110111 #A +O01110101 B 1110111 _ ¢Canry 100101100 For example, 2.6.2 Binary Subtraction ‘The subtraction of two binary numbersis performed exactly in the same manneris the subtraction of decimal numbers. Only four cases occur in the subtraction two binary bits. 0-0=0,0- =-1,1-0=1,and1-1=0 ‘InO~-1=-1, the resultis negative. Itindicates that the second numberis gr than the first one. Similar to decimal number: a peuraeeer I \When the binary numbers are more than one bit, the subtraction takes place bit by bit, which starts from the left side. The borrow of the previous subtraction is subtracted from the next bit subtraction, For example, 10100111 #A -01110101 B i oo110010 + Borrow 2.6.3 Binary Multiplication ‘The binary multiplication is similarto the decimal multiplication. Ifthe multiplier bitis 1, then the partial product is same as the multiplicand. Ifthe multiplier bit is (0, then the partial product is 0. Consider the example:1010 x 1001 1.0.10 @ multiplicand x 1001 ¢ multiplier SsTrosoe 0000- 0000-- 1010 Torio1o 2.6.4 Binary Division ‘The binary division is same asthe decimal division. Binary division has tworesults, lene and remainder. Let us consider the example: 10011011 is divided 100110 1o0o0/10011011% 100tal lectronics ;) Addition of postive and negative number: 4 84-9 step 1; Find the number of Bits required to represent the 1 >max (8,9, 1) and n=5 pa ome, gt-1>9 1's complement representation of (+8) = 01099 jon of (-9) = I’s complement of (01001) Step 2: 1's complement represent = 1's comp) Pemena Binary addition: 01000 +A +10110 +B 1110 Step 3: The most significant bt is 1, so the answer is negative, a 1's complement form. a Result = ~(00001) iti (iii) Addition of two negative numbers: (8)+(-9) 17 ‘Step 1: Find the number of bits required to represent the number, 2" 1 >max (8,9, 17) 2'_1>17 and n=6 ‘Step 2: 1's complement representation of (-8) = 1's complement of (001000) | 10111 t "s complement of 1's complement representation of (-9) = 1's complement of! s complement of (001001) t 10110 ‘Step 3: Binary addition: 110111 @A + 110110 +B 1a ¢ Carry 1101101 L__,1 ¢Camyis added 101110 ‘The most significant bits 1, so the answer is negative, aml es 1's complement form. Result = -(010001) = 17 umber System and Codes (89 ‘Subtraction The subtraction of a binary number B from another binary numbe to the addition of 1's complement of B to A ic. (AB) =A + 1's comple 3B. The algorithm for binary subtraction using 1's complements is: 1. Find the numberof bits required to represent the sign number. The number ofbits required to represent the sign number is, such that 2" '—1 is greater than or equal to the maximum of the magnitude of A; B; A ~ B. 2. Find the 1's complement ofthe subtrahend. 3, Add A and the 1's complement of B 4. Check the cary, ifthe carry is generated, add the carry in LSB position and take the 1°s complement of the result. If the MSB of result is 1, then the answer is negative; itis in 1's complement form. Ifthe MSB is 0, then the answer is positive and in true form. fer A is equivalent ment of Consider the following examples. @ 8+ ‘Step I> Find the number of bits required to represent the number, 21> max@8,9, 1) 21159 and n = 8+ I's complement of Step 2: 1's complement of (+9)= 1's complement of (01001) 0110 Step 3: Binary addition: 01000 +A + 10110 # 1’scomplement of B Tio ‘The most significant bitis 1, the answer is negative, and itis in 1's ‘complement form. Result =-(00001) = 9+ 1's complement of 8 Find the numberof bits required to represent the number. 2-1 >max@,9, 1) 2-1>9 and n=5 Step 2:_ 1's complement representation of (+9) = 01001 1s complement of (+8) = I's complement of (01000) =10111Step 3: Binary addition: 01001 6a . 101115 6.1’scorpa, 1111 * Carry ae 100000 ¢ Carry is added ‘The mos significant itis 0, the answerig form, Postini Result = (00001) = 1 } 2.7.2 2's Complement Arithmetic Addition The addition of sign-binary numbers takes place Using 2's co, algorithm for sign binary number addition using 2s complement Consider A and 8 are two sign numbers mplemeny iSpiventay 1. Find the number of bits Tequired to represent the sign number, Thenumber ofbitsrequired to represent the sign ‘number isn, such that 2 Fie let than or equal to the maximum ofthe magai i 4. Find the binary addition, 5. Discard the carry ifit is generated. ‘Consider the following examples. (i) Addition of two positive numbers: 84+9=17 Step 1: Find the numberof bits required to represent the number, 2-1 > maxi8, 9, 17) 2"-1>17 and Step 2: V's complement ‘Tepresentation of (+8) = 001000 __ | Scomplement representation of (49) = 001001 3: 2's complement Tepresentation of (+8) = 001000 Fepresentation of (+9) = 001001 ition: Number System and Codes 85) Gi) Addition of positive and negative numbers: 8+(-9)=-1 Step 1: Find the number of bits required to represent the num! 21 >max(&, 9, 1) -1>9 and’ 01000 's complement of (+9) Step 2: 1's complement representation of (+8) 1's complement representation of (-9) = I’s complement of (01001) =10110 ‘Step 3: 2's complement representation of (+8) =01000 2's complement representation of (-9) = 10110 + 1 =10111 Step 4: Binary addition: 01000 «a +10111 0B arias ‘The most significant itis 1, the answer is negative, and itis in 2's complement form. Result =-2's complement of (11111) —I's complement of (11111) + 1 (00000) +1 =I Addition of two negative numbers: ‘Step 1: Find the number of bits required to represent the number. 21> max (8,9, 17) WW 1>17 and n=6 1's complement representation of (-8) = I's complement of (001000) =o 1's complement representation of CS)=1's complement of (+9) 1's complement of (001001) = 110110 Step 3: 2's: ‘complement representation of (8) 1's complement of (001000) + 1 MOLL+1 = 111000 . v Step 2: "s complement of (48)‘complement representation of (- a =110110+1 ty Su ae ae means ad Step 4: Binary adition Step 4: Binary addition: 01000 +A 111000... «A #10111 ¢ 2's complement of B +110111 4B ‘i Seren TTia a ‘The mos significant btis I, the answer s negative, and itisin2’s EET oe teeny mate ta xe most significant bitis 1, the answer sng ”s complement of (LL ‘complement form. Batives andi, th seat aa met Result = 2's complement of (101111) =1's complement (101111) +1 (010000) +1 (010001) hay I 9 8=9+1's complement of 8 ‘Step 1: Find the number of bits required to represent the number. ‘Subtraction | 21 >max (8,9, 1) ‘The subtraction of abinary number B from another binary number iseqgn. 1-159 and n=5 tothe addition ofthe2's complement of B with A i.e.(A~B)=A+2'scony Step 2: 1's complement of (+8) = 1's complement of (01000) of B. The algorithm for binary subtraction using 2's complements as fala ont 1. Find the number of bits required to represent the sign number. Step 3: 2's complement of (48) = I's complement of (+8) + 1 The numberof bits required to represent the sign-binary numberisy "complement of (01000) +1 that 2°"! — 1 is greater than or equal to the maximum ofthe magus = 1011 +1 A:BA-B. 1000 2. Find the 1’s complement ofthe subtrahend by replacing 0 by 1 and Step 4: Binary addition: 3. Find the2"scomplement of the subtrahend by adding I tothe I'sco 01001 +A 4, Add these numbers using binary addition. 11000. ¢2°s complement of B 5, Discard the cary, ifit is generated, 1 Cary IfMSB of the esult i 1, then the answer is negative; itis in 2's co 00001 ¢ Discard the carry form. Ifthe MSB is 0, then the answer is positive; itis in tue form, Sera ae ‘The MSB is 0, the answer is positive, and itis in true form. (ab cos + Result = (00001) =1 8-9=8+2'scomplement of 9 Example 2.21 Perform the following operations by using 1°s complement Step 1: Pe the number of bits required to represent the number. method. Dei scuia9, » (@) 42-22 (b) 20-42 (©)-42-20 Solution @ 42-22=20 ae 42-22= 4241's Step 1 pea eee eer 211 > max(42, 20, 22) _ = 1’s complement of (01001) +! ae cae Q-1>42 and n=7 nOf (+9) = 1's complement of (49) +1gg) _Digital Electronics 1's complement of (422) = 1's complement of 1101001 sp 3: Bir aio 0101010 +A dab iteiti texctooncn ora, 70010011 L —! “poi0700~ The MSB is 0 the answer is positive, and iis inte fom Result = +(0010100) = +20 20-42=20+ I’s complement of 42 ‘Step 1: Find the number of bits required to represent the number: 211 > max(20, 42, 22) t-1>42 and n=7 Siep 2: 1's complement of (+42) = I’s complement of (0101010) = 1010101 Step 3: Binary addition: 0010100 +A #1010101 ¢1’scomplement of B 1101001 ‘The MSB is I, the answer is negative, anditisin complement ia Result =-1"s complement of (1101001) = (0010110) 22 (©) ~42-20=-62 ‘Step 1: Find the number of bits required to represent the number. 2011 > max(42, 20, 62) 2"1-1>62 and n=7 ’scomplement representation of (-42)= 1's complement oft =1’s complement of (0101010) = 1010101 ‘'scomplement representation of (-20) = 1's complement of 's complement of (0010100) = 1101011 | 10149. > umber System and Codes (88) Step 3: Binary addition: 1010101 6A + 1101011 +B LLL 9 Cany Troo0000 41 ¢ Camry is added —reo0001 “The MSBis the answers negative, anditis in I's complement form Result =-1's complement of (1000001) (ou1110) 2 Examples 2.22 Perform the following operations by using 2's complement method. (a) 46-23 (b) 23-46 (@)-46-25 Solution (a) 46-23=23 46-23 = 46 + 1's complement of 23, Step 1: Find the number of bits required to represent the number. 1 > max(46, 23,23) =1>46 and Step 2: 1's complement of (+23) = 1's complement of (0010111) 1101000, ‘Step 3: 2's complement of (+23) = 1's complement of (+23) +1 =1’s complement of (0010111) + 1 1101000 + 1 = 1101001 Step 4: Binary addition: 0101110 4A +1101001 ¢2'scomplement of B Tt ¢ Carry EOOLOTIT ¢ Discard the carry ‘The MSB is 0, the answer is positive, and itis in true form. + Result = (0010111) 2423 (b) 23-46 =-23 23-46 =23 +2’s complement of 46 Step 1: Find the number of bits required to represent the number. geil. a ta eesuep sep 4: Binary ation: 010 41010010 ¢ 2's complement of B 1010001 = 1010001 +1 = 1010010 111 6A root 's complement of M1149) mplement of (.gg) 's complement of (4 111g), ‘he MSBis I sotheanswerisnezaiveanditsin2 ony, form, Result 2’s complement of (1101001) 'scomplement of (1101001) + 1 =-(0010110) +1 (0010111) Step I; Find the numberof bts required to represent the number, 2011 > max(46, 25,71) 1>71 and ‘Step 2: 1'scomplement representation of (46) = 1's complementof Sep: 1's complement = 11010001 of (00101110) {'scomplement representation of (-25) = 1's complementofl = I's complement of (00011001) 1100110 2's complement representation of (~46) = (46)+1 = 11010001 +1 = 11010010 's complement of (00101110) + 1 *s complemet 2.3 complement representation of (-25) = 1's complem®! (25)41 =1'scomplement +1 of 00011001) +1 umber System and Codes Step 4: Binary addition: 11010010 6A +11100111 6B 1 1t oCany FIOLI1001 ¢ Discard the carry ‘The MSB is |, the answers negative, and its in 2's complement form. Result =-2's complement of (10111001) 1's complement of (10111001) + 1 (01000110) + 1 (01000111) =-71 ARITHMETIC OVERFLOW. When we add two positive or negative binary numbers and the result exceeds the original length of the number, itis known as overflow result. Overflow causes a sign change. Letus consider the examples ofthe sum of two positive binary numbers as Case | and the sum of two negative binary numbers as Case 2. Case 1: Sum of two positive numbers Consider the sum of +125 and +75 +125 Olliiio1 +75 01001011 titi $200 11001000 As the decimal sum of +125 and +75 is-+200; the length of the numberis 8-bit, the result is 9-bit and an overflow occurs. This overflow changes the sign of the result and the answer is wrong, Result shows that the sum of two positive numbers is negative, which is wrong. Case 2: Sum of two negative numbers Consider the sum of -61 and 43, 61 10111101 -43 10101011 wit =104 101101000 As the decimal sum of 61 and ~43 is 104, the length of the number i i the result is 9-bit and an overflow occurs. By A iy eg ox yk‘Codes arethe representa d symbols, which man ¢, iat may incl pers, alphabets, aM oN 2.9.1 Classification Computers eco ‘of Codes india data, Tedgital data3s an input tthe mag puetciecciaceer toe come mn pnts, 2269 ume punctutio of tand0. When t sane contol characters should be represented by unique ge Missoni of and Oarereleredas the code fog data is transmited over long distance, itis transmitted ne cove words, Daring the transmission process, errors may be introduced 1 tntcoret the erors, special codes are used in digital communication, ‘The commonly used binary codes are classified as: 1, Weightedcodes if-complementary codes 3, Unitdistance codes 4, Alphanumerical codes 5. Cycliccodes 6, Error detecting and correcting codes Weighted codes Inweighted codes, the weight ofadigitora bit depends on its position, For indecimal code 589, the weight of is 500, weight of 8 is 80, and weight oft Similarly in binary ode, the value oft depends on its position. Binary, BCD, 8 and 2-2-1 are the examples of weighted codes which will be discussed ‘next section the example of sel. ; complement of he exec Sle complementary code. In this code, te i excess-3 code isthe excess-3 code for the 9's comple Number System and Codes 1980 Alphanumerical codes ‘The binary codes of alphabets, numbers, and special symbols are known as aiphanumerical codes. ASCII (American Standard Code for Information interchange) and EBCDIC (Extended Binary Coded Decimal Interchange Code) ‘are commonly used alphanumerical codes, ASCII and EBCDIC codes will be “discussed in detail inthe next section Error detecting and correcting codes \When information in digital form is transmitted toa long distance, errors may get introduced and I becomes 0 and 0 becomes 1, Special codes are used to detect and correct such errors. Parity and Hamming codes are commonly used for error detection and correction. 2.9.2 Binary Coded Decimal Code (BCD CODE) Itis a 4-bit binary coded decimal number. Each digit of the decimal number is represented by four-bits, the digit 0 in BCD is represented as 0000 and the digit 9 is represented as 1001. The BCD codes of Oto 9 are given in Table 2.6. Table 2.6 BCD cades Decimal BOD Code Digit B B By Bo 0 0 0 ° ° 1 ° 0 ° 1 2 0 o 1 ° 3 & o 1 1 4 ° 1 ° } 5 ° 1 ° i 6 ° 1 { mi 7 ° i 1 1 % i 0 0 0 9 i a a p ‘Thecodes, 1010, 1011, 1100, 1101, 1110,and 1111 are invalid. The weights of Bs, Bo, By, and By are 8, 4,2, and 1. Hence, BCD code is also known as 8-4-2-1 code ‘An N digit decimal numbers represented by 4 x Nits in BCD code. The BCD ‘code of (15)19 is 00010101, and the binary code of (15),g is (1111). The BCD ‘code of (15)jo is eight bits and the binary code of (15),9 is four bits; it shows that ‘the BCD code is not efficient as compared to binary. The BCD code requires more space and time to transmit the information. The arithmetic of BCD code is also complex, A few examples are given below. (Decimal 2 6 BCDegivalent 00100110 (ii) Decimal 8 -84 _ Digital Flectronics BCD arithmetic 2 BCD Addition In BCD addition, each digit ofa decimat np int ts 4bit binary equivalent and the addition of two BC hey, using the rules of binary addition. esis ay “After the addition of two BCD codes, the result may be an BCD. Ifthe resutis invalid, itis converted into a valid BCD by ly, (Gyo forthe 4-bit addition cary is generated ater the addition 806 added to the next bit. Ong’ Algorithm for BCD addition: 1. Convert the decimal numbers into their equivalent BCD cog, 2 Add the BCD numbers using the rules of binary addition, 3. Check therestit itis valid less than orequal 09), no corectig and ifthe rest is invalid (greater than 9), 0 to the next stp a stop ~ 4, Add 0110 to the 4-bit sum to get the correct result (i) Addition of Sand 3 in BCD 3 0101 * BCD cole, +3 0011 ¢ BCD code, 3 111 ¢Cany 1000 + BCDeoky, The addition of wo BCD numbers, 0101 and 0011 is caried outusngh addition and the sum, 1000, is obtained which is the BCD code for, (ii) Addition of 8 and 5 in BCD 8 1000 BCD coded +5 0101 ¢ BCD coded 3B 1101 ¢ Invalid BCD (1101), isthe binary equivalent of 13 in decimal. Itis an invalid ie It-canbe corrected by the addition of (0110) to the invalid BCD rest 1101 ¢ Invalid BCD +0110 1 ¢Cany 00010011 ¢ BCD code of 13 Addition of 7 and 9 in BCD # BCD code of7 # BCD code of ¢ Cary ¢ Invalid BCD! +9 umber System and Codes 95 To correct the result, add OL10 10000 + 0110 “00070110 ¢ BCD code of 16 Example 2.23 Perform the addition of the following numbers in BCD (6-421): 847 (i344 i849 Solution @ 8 1000 a3 oil te OL +4 +0100 5 TIT ¢ Invalid BCD code eae +0110 Add6 00010101 ¢ BCD code of 15, Gin 8 1000 +9 + 1001 ae TOOOT ¢ Invalid BCD code + 0110 Add6 00010111 # BCD code of 17 Example 2.24 Perform the addition of the following numbers in BCD. (84-21): (15 +24 Gi) 19 +22 Gi) 91+ 81 Solution wo 1S 0001 0101 BCD code of 15 +14 oo1 0100 ¢ BCD code of 14 228, 1 1 Carry 0010 1001 ¢ BCD code of 29 (ii) 19 0001 1001 ¢@ BCD code of 19 + 22 +0010 0010 BCD code of 22 TH 0011 TOTT ¢ Invalid BCD code + 0110 ¢Add6 1 1 Caer es196 Digital Flectronics Gi) 91 1001 0001 @BCDecg +81 +1000 0001 s BeDeoge tl a Tela teiceo nn eeclas Cesena T0001 0010 « Soon, coo i +0110 0000 # Add oro sing ooo1o1tt 010 02 secong fl oor # BCD covcor me Example 2.25. Perfo the alton of the foto wing re (8-4.2-1) ( 1914171 (i) 9174215 Solution @ 19 0001 1001 00014 +17 +0001 oui 00014 - U1 it itso =a 0011 0000 Since carry is propagated from the second digi, the a invalid BCD, Add 6 to the second digit to correct the onli a 0011 0000 0010 + 110 + Adas OOIT 01100010 5 Eg at Denied pers @) 917 1001 0001 O111 ¢ BCDeod +215. +0010 0001 0101 + BCDeaie 132, 1 111_¢Cany ion 010 1100 # BCDeoie ‘The first and third digits are invalid BCD. Add 6 to both the digs 1011 0010 1100 +0110 0110 # adds Lu 1 ¢Cany 7 0001 0010 10010 ¢ Propagaet 0001 0001 ool 0010 ¢ BCD coded BCD Subtraction The subtraction of numbers is nothing but an additi second negative number with the first number, ie., A-B=A4(-B) In other words, the subtraction of numbers is the addition of a signe Theaddition of signed BCD numberscan be performed using 9’ sor 10° ‘pie negative BCD number can be expressed by the 9's or 10's comple BCD number,’ umber {CDsubtracon using 'scomplement bacon othe second nunbet ace utnunberistheatstomscomplementof te secondnumber wih sar per Thc3'seomplenentotadscial ure ixcisined by SUDAN sa thc dectnal number om. The 9's complements af he dein Sos re enn Table Table 2.7. 9's complement of decimal digits Decimal Digit Decimal Digit | 9'5 complement x complement 9 1 8 1 4 3 2 a 0 5 _Ngorih for BED subtraction using 9s complement: {) Find the 9s complement ofthe subrctr. (i) Perform BCD addition of the ist number wth the 9s complement ofthe second mober Gi) HTear is generated thenthe results postive, Add the carry tothe resltto eth correct result. Ircarry is not generated, then the resus negative fd itis in scomplement frm. Tookat few examples (a) 8-3 8-3 =84+(0's complement of 3) 846 1000 ¢ BCD code ot 8 +0110 ¢ BCD code of 6 THO’ ¢ tavalid BCD. 110 + Adds u T0100 Loot + adie cary to LSB 0101 ¢ BCD code of 5 2 ©) 3-8 aaa 3-8=3+(0'scomplementof8) 1 =341 +e 4-1 4— 1 =4+(9"s complement of 1) +8 ; 0100 # BCDeade of 4 +1000 ¢ BCDeode of 8 T100 ¢ Invalid BCD code. +110 # Adds 1 Toorsoe) Digital Mectromics _ s complement Su 4 (a BCD subraction using 10's complement Subraction gp, (Br st st namie isthe dition of 10's complemen oh ay umber tne The 10 scomplemen' fa decimal mga rane wath "s complement of the decimal number, The ge Praplements ofthe decimal digits are given in Table 2.8 aa Table 2.8 9's and 10's complements of decimal digits pay 9 |e [Decimal | 9% erin! | plement complement | aig | complement | cgi) 0 9 10 5 i sen 1 8 9 6 3 : 2 : 8 7 2 © 3 6 7 8 1 a 4 5 ‘ 3 ° 2 “Algorithm for BCD subtraction using 10's complement: 1. Find the 9's complement ofthe subtractor 2, Find the 10's complement [ie., 9's complement + 1} 3: Perform BCD addition of thefirst number and 10’scomplement of hese number, 4, If carry isnot generated, then the result is negative, and its in jp, complement form, fcarry is generated, then the results postive, dca, the carry to get the comect result. Let us look at afew examples. (a) (8-3)=8+.(10's complement of 3) =8+ (0's complement of 3+ 1) =8 +7 1000 # BCDcode of § 40111 # BCDeodie of 7 TI11 ¢ Invalid BCD code + 110 ¢Aad6 11 ¢Cany XO101 ¢ Discard the cary 0101 #BCDcodeofs (6) G=1)=4+ (10's complement of 1) =4+ (9's complement of 1 +1) =4+9 0100 ¢ BCD code of 4 +1001 ¢ BCD code of: 4 (10°s complement of 8) {3 +0°s complement of 8+ 1)=3-+2 0011 # BCD code of 3 40010 # BCD ode of? ‘0101 ¢ 10's complement of 5 Carry isnot generated, hence the result is negative. Result=—5 (a) (—4)=(1 + 10's complement of 4) =14(0's complement of 4+ 1) =1+6 0001 # BCDcodeof I 40110 #BCDeodeof 6 OLLT ¢ 10'scomplement of 3 Carty is not generated, the result is negative, Result =—3 Example 2.26 Perform the following subtractions of BCD numbers using 9°s complement. Noes 4-8 © Be Solution (a) (8-4) =8+ (0's complement of 4) +5 1000 ¢ BCD eode of 8 +0101 # BCDeode of 5 TION ¢ Invalid BCD code +0110 #Add6 1 Carry ae TOO11 LL—41 ¢ Add the carry LL Cary % Men 0100 #BCDeode of +449s complement of 24) 475 Q110 1000 # BCDcode or 6g soll 0101 ¢ BCD code of 75 Carry ror TTOT + Roehiedisis einai +0110 0110 ¢ Add6tocach digit *Dy, L 1__¢Cany Toor 10011 Lig Lest @ Ada the carry u 11+ Canry 10d 0100 _¢ BCD code of 44 (a) (24-68) =24 + (0's complement of 68) =24431 0010 0100 BCD code of 24 +0011 0001 ¢ BCDeode of 31 0101 0101 ¢9'scomplement of 44 ‘Camy is not generated, the result is negative. Result=—44 Example 2.27 Perform the following subractions of BCD number yy 10°s complement. @s-4 () 4-8 Solution (@) (8—4)=8+ (0'scomplement of 4) 8-+ (9's complement of 4+ 1) =846 (©) 68-24 @ 4-6 1000 BCD code of 8 +0110 + BCD ode of 6 1110 ¢ Invalid BCD. + 110 Adie 1000 0001 0010 Add3tocachdigit, > 0011 0011 9011 ua 1 Excess-3codeof 812 > 1011 0100 0101 ‘9's complement of 812 = I's complement of (1011 0100 0101) =0100 1011 1010 (0100 isthe excess-3 code of 1, 1011 is the excess-3 code of 8, and 1010s the excess-3 code of 7. ©—— nal 2.98 Gray Code age, Decimal number. 01015, te repreg eae Fe cee RIES ikon aw distence code TS cry 220 malts ey cater forte lowing dial umba codes. Tis Ce ne bit position: ey @ ©) Bore rare aatecnmea. | oui se NN pe, Becalse ofthis he Gray codes ogo a) AS 1D: ) 14.9= 110), . _ By=1-By=1,B,=1,By=1 |, By = 1, Bo=0 ( Ms application in anag-10-digital oy ie decimal numbers, 0015, is given nin Gy=By=1 G G,=B:@B)=10 161 hi tions, but BOB, =18 B,@B,=1® ‘Decimal Go= By @ By Go = By BB Ge | aise Gray code of Gray code of rea als ee (©) B)yo= (1000). rielomesbas|oized| Fels | 0 By 1, Ba =0,B) =0,By=0 Sel merc | | tie iy peer a (et to pretnaee| to 1 fei |e at faloteel tal co | 0 alesis | 20.1.5, Gray code of = 1100 Example 2.31 Find the Gray codes for the following binary numbers. oven devimal number, one can notice a ewocanscutve digi fecccme Bing a) 11001100 (01011110 ayeove changes from 0101100100; thgey | Solution (@) 11001100 () o1o1nit0 By =0, B= 1, Bs=0, Bu= ly ‘we examine the Gry cecbitftie Gay code canes changes from 6107. i erg netmost tly. Ths isthe primi characteristic of the Gray eo, Binary-to-Gray code conversion ‘eisificuttoremember ihe Gray code of each decimal number as compared eet Bo So ‘inary code Hence, wit the binary code ofthe decimal number and then cones iy it into Gray code by using binary-to-Gray code conversion technique, Ti Ge=B,® Be=0@1=1 generalized method of conversion for N-bits binary to Gray is as follows: Gs = By @ B: Gyr By (28) G,=Bs® B,=0@1=1 G,=B,8B,= 1814 Gr= B® B,=18 G,=B,®B,=1@0=1 Go =B, ® By=0@0=0 ‘The gray code is 10101010. eats ‘oa expan, N= the Gray codes bined by using the GB aeumber System and Codes 108) Gray code GL Glo me] ne generalized method of conversion for Nits Gray-to-Binary codeisas follows a (2.18) o| o By_2=By=1 @Gy—2 19) ! o}o By=3=By-2OGy—3 (2.20) 2 0 0 Pe aslaelete cir ce tet Pe Sasa ne ene of ' 2.22) Gael cali dialaeledor| Bich so% (4 223) Tc etal esa eS eat tH ciclo the Binary codeis obtained by using the following : pepepo lx) 1 | 0 og ti re iisieandetey ta Opel, 224 L 2.25) «ty Te ei binary coe represent te decimal umbers, 010 15-Theg 0 i cen ofthe decal TOMDer re git eo (226) tn ca inten 27) 5 | example 2.33 Find the Binary codes forthe following Gray codes: Tuble216_ it binary code and ts Gray code a at see aaa Fase . oS [Sane FRET ET TG Te |S Gren raycotts1000. (0) Given Gray cadet 1010, ofofofofofo}ofo | Gs=1,G,=0,G,=0,G)=0 G5=1,G)=0,G)=1, G0) ofofofi}o}o}oly 2 acae oes Pleciaieers iene] 5 | hal ay B= ®G,=100=1 B,=B,@G)=100=1 oleralse | SoHer cho ae 5y=B2@6;=10 2,=2,06,=1@1=0 apereatiy: ara adil c(i 2 Bo=B, @Gy= 1 By=B, ®Gy=0@0=0 earns 1 Roel a Mi ‘The Binary code is 1111 ‘The Binary code is 1100, shies en iaiendl st.) js0, 0, (©) Given Gray codes 1111. Looe latsleds| ov |. oo; ln G=LG=LG=16 Lele ot feat alo. | a By=G,=1 wate rvel 05) telaet | des B,=B,0G,=18 We lle cla Pod abate nO scl neds | ct By=B,®G)=1@1=0 o r Aten | earch ghey) ‘The Binary code is 1010. \ ida. Leptin isi Ltt 2.9.9 Seven-Segment Code Gray-toBin 'y-to-Binary code conversion Inmostof the applications, seven segments are used to display the | —"— result. Binary or decimal digits cannot be dispalyed directly over } Inatelephone communieation, ae ion system the, ‘ {Gray coe. Butane reciente SEY betransmitedinthefom | the seven segments, The seven segment display includes seven / aoe isnecessary tocomer he Gry difficult to decode the message ‘Segments, which are refered as a, b, c,d,e,fand g. The segment |__& 'y-to-Binary code converter, ‘into its equivalent binary by using will be ON or OFF according to the input data and the type of | noe ee abe serenseaments ar ofwotypesa) common anode . common cathode type. The seven segments are shown. inthe nuceceR gure ae oh aaaDigital Blectronies_—_ ea ‘Common anode type Ina common anode type seven segment, the anode of lighten, smnnected togeter 10 Ve. When the input iso, grein dita penne (segment) are connected to i » the coreg ge ,/tS,*,etc. Inother words, alphanumeric codes are the binary representa Om Se geand EBCDICare the examples of alphanumeric codes. an a umber System and Codes 4441 segment is ON; ie seethseement cove for common anode types ven in Table 2 19 Table 2.17, Sovensegment code of decimal digits and hexadecima}g ASCII code ce ieee matt Ta [OTe TATE LT Te Tap gets) Acme cad tices n mow of te microcomputers 8d of efefe fe fe fo Ps Fr TARR) onan anna mations vat steele Wha? 28 1 “sifio attl al ja os ansible ede groups. ll the keys ofa keyboard are represented by 7 bit binary 3 ° Jo Ofodi (4 bola ae ‘eulcomputrs, and stored it the memory. The ASCI code and its octal an 4 tfofof1]fa fofofy % vexadecimal equivalents are given in Table 2.19. : Cabs sear eta Dl 2p 8 | 4 Character |7-Bit ASCH Hex] Character [7-Bit ASCH | Octal |Hex 8 eee eae | 21. aoa 5 | 1000010 42| 2 | tortor | 152 | 5a a D 100 0100. 44 1 101 0001 | 161 | 31 SI ts E 100 0101 45, 2 101 0010 | 162 } 32, Ina common cathode type seven segment, the cathode of light emmiting ding | F | 100 0110 46 3 toi 0011} 163) 35 (eam) areconnectdtngetherto round. When he inputs 1th comespn | a | woo 47| 4 {1010100 | 164 | 34 SamentisON:and viene aptin iecreponding segment wore | | ¥ | 100100 fio | 48] 5 | ror o1or | 165 | 35 ‘seven-segment code for common cathode type is given in Table 2.18, | f 400.108, ey = tor Diigo Table 2.18 Seven-segment code of decimal digits and hexadecimal equiva rays] 00 1B AB e 1110004) ei ea cae TTS Te PoP amwee]) |e | toon | is [40] suann | toro | a | 2 | 1 op ee ea elena 8 a N | 100 1110 4B ror ino | os6 | 28 2 Te arses tea |' 1! |, | 2 eee ar ( 101 1000 | 050 | 28 3 TE ema peekep | pa | P| 100 0000 sof + | ior tom | 053 | 28 4 OH al cetindl DN Sear bey R @ | 100 001 st} s | 101 o100 | oaa | 24 3 1s al met te | 66 R | 100 0010 52 . 101 1010 | 052 | 2a 6 Sho etal a 0 Be S| 100 0011 33 ) 1011001} ost | 29 : fale teliaal eles lin)” BE T | 100 0100 34 2 tor 1101 | 055 | 20 8 tLe lata iah sy, ew EO y 100 0101 55 ' vor iit | 057 | aF 9 1 id ean ey sa ifo FE 100 0110. 56 101 1100 | 054 | 2¢ 1 1} o F6 w 100 0111 57 101 1101 | 075 | 3D. is cn x | 100 1000 | 130 | Se [exerenn| ror uot | 018 | op i || 101 1010 | 012 | 0A eee seem alphabets, andspecial symbols Tacha teat consisting ofmumercas | FBCDIC alphabets and special symbols tog, ismeeessary to have binary codes ft Extended Binary Coded Decimal Interchange ate called alphanumeric codes ‘code. This isan 8-bit code and so, ithas 2 26 uppercest Code (EBCDIO) is anatphanumeric 256 possible code groups. The EBCDIC ‘Acomplete alphanumeric, codes Jevers, 10 numeric digits 7aNumber system and Codes _ 86 ebit | Character] 5 “pows hat heres erorinweducedoverthechanael tal ncoic aa Ceaser smaitshowatio sroducedoverthe channel, etal ae ne erie changed over hePal Fore mf tio0900! |G | mtotso | ee ane 2.21 it mesage wih even party and ol pay 0 = www} 2 Yon | 7 | unan| a icv | Oi prin coded : inio0010 | 8 4 PL Me| Ms] Mi Ma |? | Mol a [ats [Mo p | sre0ot00 | § 11111009 joo | 9 eet io] 12 [° E 11000101 T uw TNT 100) tlololots joo olo\t Ernie | w_| tvont@e | BLANK | tone 1491 oye |e \oll coal ela Fe fy. fatgeian | ot) oteoien +) eel clan |e eon etalaianlae So resin een ee aus Leek etl malcas | at hah ee Rea racer luo enivondi| 2+. *!f o}botiy ofolifofs | syals ye dy 1 [ranoet | yf anon | $ | ototion ofojryrtetstel sys la ig eae eet pancou | foe | ONT fo yee ean a aortic] be euat@onk| ps3) oiorst 1 /te[oedl mile )ets at an Me of trosoran | > 1) | 1saioor 01100000 baa ees PS hata feed ess di MO icretotl le amen aLegO te |, rae) Oh oat | efo: fem | eyes ate ea o =| tantaito’). 3% seen " o1t01011 0.) tea [ot /eee ya etl ete eo 4 | tnttoroo |= | atte { [1 janhoilet |) eam 1 ao: Vio at a ‘ tis setae a 2.9.11 Error-detecting Codes "The I-bitparity code word can detect {-biterrors,butit cannot detect the Tocation of the error or correct the error. "The circuit that generates the parity bit at the or ey enn caled party generator and thecircithatchesks the PaNiS A tir oceiving end is called a parity checker. The designs of panty generator and parity checker will be discussed in Chapter 4. ‘ Inga commonicatonth digital dais sentoverelepone ines using fea nas codes, During the transmission, beats of mois signal, may become a Pin pecome O, and wrong infomation may be received at the destination, Thi oblemsof communication is overeoneby wngeror- detecting codes. Thesimple prove detecting codes ae: () parity codes and (i) block parity codes. vt tre ay ace ec Usually ASCII codes used for ending digital data overtelephone lines. The |-bi rare than two bits, the parity of the message may be unch ‘or more than I-biterors may occu in transmitted dat, To detect these er1or Tooker eannot detect the error. This imitation of parity code is over party bicomalremenes aee “Atthereceiving end, party [| _certainextentin block parity codes. Inthis technique, SAE SE vile eee aoe a Mga Me M9 "Ms; | information as a block, each block consists of Mo where P is a parity bitand My. t0Mo are N message bis. There are two | FB 2.3. Party bits can be assigned to both types of parity: () even parity and (i) odd parity block consisting of four words, each word c ‘For an even parity code, the total number of Is in the parity code word is eve: $ i ee sy aS iy cre te ikea AE eh ic wd soi hl a cage with even parity andoddperiyisgivenin Table 221, -Thosinle part bitcode can detect singlebitemos the “ bi tuitcannot be detected. Forexampl assume the even espe teT Co oe eter ea of received code word is odd, it shows that a bit receiveris 1001 1, the pant oe But ithe receiving coe Wrdis 100 tenth pean io ohne pay ofrecivecole4 ~ sitrcevestheblockof dataand checks the ‘The receiver cite 1e parity of rows and cx Parity anda. rere cage in he PAE of ONE TOW and on ‘hy iseran F ante poston of or termined by yy aang etus consider Fig. 24 “hey ror 00010 ot 011 0|1 < Parity eror 1000 1000/0 orto 10100 Tigo oroilt f arity error fig. 24 Block code with 1-bit error ‘There isa parity error in row number 2 and column number 3. The posi ovis shown inFig.24by dark shadow. This can be corrected by complemen! tho er bit fthere isachange of parity of more than one rows or column Ts ee umber System and Codes _ 445 Linear block code Fhe sie of linea codes bits, where = +r isthe number of message 1 a liber ofcheck bits, The block code is designated as (nk) code, The "whether the error is present or not withthe help of check bits are represented by a mattix recoding oflinearblock codes Linear block codes are represent Encodes thesizofthemessageand inthe ize othe ina oes code (n= K+). The block code C isobtained by the multiplication of message bits sid the generation mati MxG 2.28) white doing the matrix mltipication, MOD 2 operations are used. The generation matrix is constructed as Gath: Alen (2.29) canere is the identity matrix of order k and A isthe arbitrary matrix of order (kx. “The arbitrary matrix is selected such that the resulting code should be capable tno tan|bitemer has occured, as shown in Fig. 2.5 st todetect and correct errors at the receiving end C=MxG 100 TH10 O101 01 Tf eariyeror ie 011 0001 | 0 x 2.30) 1000 0110] 1 [C102 = Gy) = (MaMa «Mad Uh AY 2.30) 1000 1000] 0 For example, consider the matrix 119 1010/0 1 Fig2.5. Block code with more than 1-bit error and message bits are (01 1) "The linear block code C = (M1 x {G} Her the pry enor sineolnn nubers3 nd 4. This error canotbe cone (Ma: AT because there is no information about parity error in rows, and hence the postin of error bits cannot be located. 100 5100 : =[011)x{ 010: 101 2.9.12 Error-correcting Codes oor: tt The ing codes se rmccra esi codes canot define the poston of an error and cannot ome Tce snedoracoe which can detectas well as coret ther detect ion capability ofa code depends on the nuke of entra bits that are added ina message to get the code words, which increasestt distance between adjacent code w Ha isthe shortest distance between any tage nt distance of coding shee dyin the numnber of errors that canbe two distinct codes. For a minimum distan that can be corrected is (dgi~ 1/2, is (djr~1)and the number of ene =(0x11X0@1x0,0x081x1@1x0,0x0@1x081x1, 0x1@1x1@1%1,0%01x0 1%1,0x0 1x1 61x11 =10©080,08160,08081,00101,00001,081 81] =[011010} Decoding of linear block cades The receiver circuit receives the linear block ‘code of nbitsitdoes not know the transmitted message. Thereceiver checks whether ‘or not an error is present in the receiving message with the help of an matrix, The receiver circuit calculates the parity check matrix, H=(A":1) aera ‘ee isthe nity matrix of rer ran Tis the transpose fmt A, ye ak aaAVG. Digital Mectromies ‘The parity check matrix, H, and the transpose of the received mae snug ti dsted wheter theres SHEE SCOT orga trultiplicaton (H > R) is zero, then the receiving MeSSABe is Correct, cg there isan error in the receiving coe. hig Error correction The error correction capability of a code depends, ‘minimum distance. For a (6, 3) block code, minimum distance is 3, it cay Stentor and coat herr. The cometon proce 8 8 flog 1. ind the syndrome matrix. Itisa row matrix and is calculated as S=RH™ 4 xy ‘where Ris the received code of order (1 x1), HTis the transpose of check matrix H of order (07) ™" 2. Match the row matrix $ with the ow of. The number ofa 109 Whe, match occurs gives the eror poston. ‘ For example, if matrix § matches with the third row of matrix 7 then the ey is at the third position ofthe received message. Forexample, letusassume that the messagerectived by the receiver R=01 jy and the matrix ‘The parity check matrix His calculated as follows: 111: 100 H={AT:1)=|001: 010 011; 001 R= [011000] 111: 100 xR =1001: 010] O11: 001 0 1 wel? 0 0 0 =10@101600080, = 010} (xR) is notequal 107210, . —— __ uber sytem and Godes_ : : serxst'011000}! 0 = 100181 ©06080,08001808060,08161 02080) =(010) Syndrome matrix S matches with the S® row of H which shoves thatthe errr ixartne 5" postion in the received message R. The correct result is obtained By woking the complement ofthe 5* bit ofthe received message R. Conrect received message =01 1010 Example 2.34 Find all the code vectors for the given generator matrix of & (63) block code, 100: Ow G=|o10 : 101 oor = 110 Solution ‘The linear block code C= [M] x {G] 100: On sine M=(000},C={000}x|010 + 101 . ool: 110. @0x080x eos italy — M=(001),C=(001);x1 oa a 100 = ot] eprt.c=(01Nx/O10 101) =101101 [oor : 110] fio: o1 wa(100,c=1100}x]010 + 191/=1100011) oor : 110) fioo : Olt) wepo1.cetonx|o1 = 101/=[01104 oor : 110, 100 : OW] me(110,C=(110}x]010 : 101] =[1 10110) oor: 110 | 100: 11] | Taiiee ie paca let iow aa an | ‘Hamming code araming code detects the eroraswellas locates the position of the error, state rococo. scons ding parity bitsinan-itmessage ‘et of Hamming code i 1, hee isthe numberof parity bis aden nessa Thenumbeof pty bit depends upon the umber of messages Fa message, thenumber of party bitsisk, Te value ofk must be chosen suhthi Montel For at mesa he ramber of pry bi i 3. ation parity bitsinthe Haming code cores gos ponds toan ascending tw0(2,2122),.) Te hesnot iy band nage bts genes by Me Be! he, 2B Binar yuival 0 1 H oe Ment 11 110101100 ont oi oot Hanmig 6 wi Al Hg 5 a parity bits Ps, Pa and P, depend upon i 7 Procedure to assign the vale tothe pay big ig 2 message bits: TH * Find the binary location of the mal E28 folly: = Check the position of 1 in the big * Check the bit’s location, which equivalent of parity bit, hy the binat?, rer System and Coes For example, assign the value t P inary Tocation ofthe parity bit Py is 001 + position of 1 in the binary equivalent is Py 1 postion of 1 at dis found in bits Ma, Ma. Mi, Py roceven parity, Hamming code assigns the value to P, such thatthe pasty of Ma Mae Min Pi is even. + rod parity, Hamming code assigns the value of Py My, May Mi Pr 8 0 such thatthe parity of ‘Assign the value to Py + Binary location of the parity bit P; is O10. + Position of 1 inthe binary equivalent is By, 1 Position of 1 at by is found in bts Ma, Mas My, Ps For even parity, Hamming code assigns the value to P, such that the parity of MaMa, M,, P2is even. ‘ror odd parity, Hamming code assigns 1 Ma Myo Mis Pa is 0d. the value of P, such that the parity of Assign the value to Py ‘Binary location of the parity bit P3 is 100. + Position of 1 in the binary equivalent is b. «+ Position of 1 at by is found in bits Ma, May Mas Ps For even party, Hamming code assigns the value to P, such that the parity of Mg, Ms, May Pyis even. ‘ror odd parity, Hamming code assigns the value of P, such thatthe parity of Ma, May Ma, Pyis odd “ct the receiving end, the Hamming code bts are separated as message bits and parity bits. The parity ofeach group is checked and it assigns the valle as O ifthe purity iscorrect, otherwise itassigns the value as 1. Ithe assigned values ofall the froups are zero then there is no error, otherwise there is an error. The position of an errorin the receiving messages defined by the digital equivalent of (Cs, C>, Ci). ‘where C; is assigned the value of group one (Ma, Moy Mi, P;), Cais assigned the value of group two (M2, My, Mf, P:), and Cs is assigned the value of group three (Mey Mss May Ps). Example 2.35 Determine the single error-detecting code for the message code 1011 for even parity. Solution Given message code is 1011. (i) Find the number of parity bits () required ecek Dentkel Deaektl 30 prone Bg Be By aaa umber System and Gobe_ 1 it number i 1 101 100 O11 gig Gi) Position of parity bit Binary equivalent Bit number By By By Be Bs By Bs Br By Paris pisaryequivaleat 1001 1000 O111 0110 101 0100 0011 0010 0001 Party its «| Bh. eee aaa Mi My, a ee PMP, Pi Messagebit Ms ‘Hamm M; Px My Ms Hamming © pissschthatthe parity of acodeiseven, | cach hat the parity of (Ma Ma, Mi.F,) 8 even i ol ar assign the value 1 P2 Such that the parity of iy Assign the valve to the parity bits such that the parity of the code is od party of (101 P3)is even, P2=0. Assign ts a ‘Assign the value to P, such thatthe parity of (Ms, Mg, Ma, Mi, Pais odie. My,MzsP3)iseven, ic. party of Ig) y8 | parity of (1110 P,) is odd, P, =0. Assign the value to P2 suc thatthe parity 4 ‘of (My, M3, M,, P2) is odd, i.e. parity of (100 P,) is odd, Pa: Assign the onus to Ps such thatthe parity of (My, Ma, Ma, sod je. paity of (10 Assign the valu tothe parity the value to Pi (UPpiseven, Pi MyM, Pp isevens ie to Pa such that the party of (Ms iseven, Ps ss i ‘The Hamming code forthe message (1011) i610 if apis odd, P= 1. Assign the value to Py such that the parity of (Ms,Pa) is rror-correcting code ‘5, parity of (1 P9) is 044, Py =O. ample 236. Avansnitersesasinglceor-comecting cod foe meng : fale evenage eens sega 11010,chg | ra Fo forthe message (11010) 8 101011000 and coret the ero. es SOLVED XM as Solution Example 2.37: Perform the following: “The message atthe receiving endis 1110101 (i) The format of Hamming code is Mg Ms Ma Pa ee eas Seve FAD24 sa iy Check the parity ofthe group and assign the value to Cs, Cand Cy, Cee eect Parity of (Ma, Mo, My, P,) = Parity of (11 1 1)= even, hence C; = 0. (e) Encode the binary word 1010 into 7-bit even Hamming code, Party of (Mi MG, My, P2)= Patty of (1 11.0) #even, hence C, =. ain arity of (Mz, Msy Mz, Ps) = Party of (1 1 1 0)#even, hence C; “a (5531)p— 32614 + (100),0 CCC, =(110)40and therefore, an error is present atthe position oft ‘Convert octal to decimal: decimal equivalent of (1 10) =6 (5531)_=(2950),oand (3261),=(1713)j9 (refer octal to decimal conversion) CConectinessage is 1010101 (5531), ~ (8261), + (100)19= 2950)i0~ (17130 + 100)i0 = 03370 Example 2.37 Determine the single eror-correcting code for the message (0) Conver: tae eae i aie6, ane ictiieaeed, “The integer part of (19.75) ois 19 and its fractional partis 0.75. ‘ Conversion ofthe integer part of decimal numbe; Solution Given message codes 11010 (Find the numberof parity bit (A required denskel este kaa ‘The length of the message =, ntk=544=9 (9)i9 = (10011). (a) (5531) ~ G261}s + 100).0 M PoP)ae ea te inane —— oa i part decimal number: “a nf aco umber System and Cd heaion Sa oo wees *MsB 2's complement representation of (17 ; complement representation of (-17)9= 2's complement of (+17) oie 1 +LsB = 1°s complement of (010001) + 1 ie = 101111 ring +12 = (HOO 1), ( frample 2.40 Perform the following subrractios using 2's complement ai (FADD - method titel 4x6 + 1516" = (62674),, {i (0011.1001) = (O001.1110) Gi). Fp She Solution i) 011.1001 —0001.1110 1's complementrepresentation of number I's complement of (000.1110) 110.0001 *s complement + 1 s complement of (0001.1110) + 1 110.0001 +1.0 2's complement = numbers into decimal: wert the following Example 2. ji) (11001101.1 ouecp) — a) | ND; ee ti) Gn, Zina Binary addition : 011.1001 A 1001 0011 1000. 0111 + 1111,0001_¢ 2's complement of B (938.710, +1111,0001_ x24 0x2! + 1X24 1X2 +0X 240x284) SO : 41X24 1X D+ 1X27 +1 x2? LE ee Result i car Solution i) 19010011 1000.0111(BCI iy (1001101.11Da= x dep 444846441 nga ee ae oe aici = 205875)i0 ‘seat es Eas v4 : Gi) (CE S)5= 15x 16+ 12x16! +5 x16" Given message code is 1010. i‘ i = 2073125) (i) Find the number of parity bit (&) required Gv) Q2)g=4x543.x5! 42x57 dentkel =o edektl Example 2.39 Write the sig jtude 1"; Yt pt k=3 cage Eee 's complement and 2°s complemes Tie hee e 495 (i170 Position of parity bit fy Solution () +95 =(+95)io= (1001.1), Spenappne rennin of 19.9) = 01001. 1 Seomplnest representation of (49) = 01001: ‘complement representation of (+9.5) = 01001.1 Gi) (79 = (Lo000), Pinna reeseniaton of 17) = 110001 of (-17),pean 0 sta te Ty OF 1, Assign th “101 s) is ever Pa = 0. ; ve, it HEPAT message (1010) is LOLO010. erage eae PO Seg | Temes 0101010 SUMMARY sate mmber of synbols sed; MIME system, ‘sont iso ax ae HE >~ cima nme syste 5 pay mabe 5 oa mumbe ste Sema ae 8 ema pein ny nr das Te information given by compere 0 va Cae a hina eos mun. hee a de se emis atiy emer mUNbe on on eggs pant. » aa woe methods wet represetsgn-inary numbers 1 sign magnitoe representation 2, re emplement representation 5.2 complement represeiation «Insignia epesnation, te mos significant it represent he sin ae ps epesent its magica. When the most significant bts sreivcguve and we the most significant bits 0, the sign is poste «the ['sconplenent of binary numbers obtained by subtracting each bitty fuer fo 1 The I's complement of Ois 1 O= 1 and the 1's complemen Tis1=1=0 «The 2's complement ofa binary number is obtained by adding 1 to the Is complement of the ins) number. The rules of binary addition are given inthe following table. A B__[ Sum [Carry a y 0 0 0 1 1 0 1 ° i . be 1 0 1 * The rules of binary suk binary subtraction are given in the following table. Borrow 0 1 0 0 amber Sytem and Codes _ Subtraction of a binary number B from another binary numiber Ais equivalent to Subvigtion of 2's complement of Band A, ie. (A ~B) =A + 2's complement of B «eitne commonly used binary codes are classified as 1. Weighted codes 3 Self complementary codes 3. Unit distance codes 4. Alphanumerieal codes 5, Cyclic codes vor detecting and correcting codes ‘s-There are two methods of BCD subtraction: T'BED subtraction using 9°s complement J. BCD subtraction using 10's complement “e-zhe 9° complement of decimal number is obtained by subtracting each digit of the decimal number from 9. «he 10% complement of a decimal number is obtained by adding 1 with the 9's TBmplement of the decimal number. «tne Gray code representation forthe decimals 0 10 15 is given in the following: He eee Gray code Decimal Gray code ‘ict |G |G 1G | & | “ee |G |G |G | Ge an Ce es ee ee ial SOs Dao a 9 | dy lode jaa go Peel a ee aoe on) roe ee ae a wooo er (0 a a PO Var ial fa Oe fis all eh ees dead feamay)s eat! goon gel sana eof eute| sta ian ia tie aaa pn | co fect) ont] as se semmmmmmemms KEY TERMS AND DEFINITIONS Smee Number systems A number is « collection of symbols. Each symbol's value is a function ofthe type of system and its positon. All the number systems are positional because the value of a symbol depends upon its position, jgned binary number ‘The numbers with a positive or negative sign are known as signed binary numbers. 1’s complement representation The 1's complement of binary number is ‘obtained when each bit of a binary number is subtracted from 1. 2's complement representation ‘The 2's complement of a binary number is obizined by adding 1 to the 1's complement of a binary number. ‘Codes It is the epresentation of information in a particular format. The information ‘may include numbers, alphabets, and symbols, which men and machine can recognize. Al the computer systems understand only the machine code, the basic property of ‘machine code is binary in nature,poniss_— iit Be It is the 4-bit bi a oo pcp code) Naty cog, i cod Prapreteand by 4b, oe edo O01 ON eee "ty Beith etal a wee coco il inber i oe Bene oak arnt ee eae TAT ee we FY STP eto “ay, be sonia lof Cit. The me nal number is repres ee Fr Te oie dein mer epee yal am co te iE BCD cose, CAC i of deny ge imi ach odes ae known. 86 Sit BCD oy hy tena eed swe foe string te 807 Magnetic ype fh i anc sina ii ©)- Ever code OUP has wo I, Theatr hc ote wel fore detetion, Py ease wisn vied THU BCD coe. Each digit Of the dina Lepoel we 7 bits are divided into two subj by 7 inary gis. The BrOUPS, G i nent Bb) nd re ws SH Ce i mamer = jas of only one 1. This code is also known as sy Eh sabrupconsss of Hl mas soe coe. reseSowde [BCD cade or by ang 3 t0 each di Gayeoie Gay codes: 4bnuneic cn; decimal numbers 01015 ae Satna cle. This cole is aso known as unit distance code becaute jy ect co iflerin nly 1 bt poston. The Gray code is an unweighted ca, Ah br pos inte cal rp do no have any specific weight assigned io th, rordetng codes In cgtal communication, tbe digital data is sen ov ee telephone lines wing feet inary codes. During the transmission, becases tvs sil, muy Become ToL may Become O and an incorcect information my be vd atthe desinn. This problem of communication is overcome by wi rordetetng codes. The simple eror-detecting codes arc: (i) parity codes and (i ‘lock parity coves. amofifed BCD coe. Tis code is obtained by adding 3s gy, git ofthe decimal number, I EXERCISES Review Questions 1. Whats the adi, unter jase ted inca of dina, inary, otal, and heradeciaa ot ; 3 What do you mean by ‘sal and hexadecimal numbers over binaries? ‘subtraction with sui tion with vitae Number System and Codes 4277 4, Explain the role of codes. \What is BCD code? What are the rules for BCD addition? Explain with suitable example, What is excess-3 code? Explain the rules of addition of two exeest-3 code numbers. Find out the BCD, excess-3, and Gray code forthe decimal numbers 0 t0 9 |What do you mean by self-complementary code? What are the two self complementary codes? ‘Write the Gray code fora bit binary number. xy code? Give the advantages of Gray code over binary code 10. 1 12. 13. What is 14, Explain even and odd parity codes. 15, Write short notes on the following codes: (i Excess-3 code (ii) BED code (ii) Gray code (iv) Unit distance code () S:bit code (si) Biquinary code ‘What is a linear block code? Derive the mattix equation relating to K-message bits, neoded message bits, and the generator matrix for a linear block code. 17, Explain with examples, how Hamming code is useful for detecting and conecting errors in digital data transmission. 18, Design a BCD to Excess-3 code converter using truth table, K-maps, and logic 19. Design the following code converters: () Binary to BCD (Gi) Binary to Excess-3 (9) BCD to Excess-3 (vi) Binary to Gray (ii) BCD 10 Binary iv) Bxcess-3 to Binary (vi) Excess-3 to BCD (ili). Gray to Binary Problems. 1. Perform BCD addition of the following numbers: @) 24436 Gi 08 + 10 Gil) 106 + 305 2, Perform the following additions of BCD numbers: (@ 801 +205 Gi) 99+ 10 3, Perform the following subtractions of BCD numbers using 9s complement: @ 9-2 2-9 Gi) 33-77 1-3 4. Perform the following subtractions of BCD numbers using 10°s complement: @ 1-3 3-7 Gi) 36-69 ) 69-36 5. Perform the following sublractions using (i) 1’s complement method, (ii) 2's ‘complement method: (11010), ~ (10000), Gi) (1000100), ~ (1010100). 6. Perform the following operation: (738), (123) + 100)jp aoe $ 7. Convert the following decimal numbers to binary: Aa spats (© (1206259 i), 120828),9.0 8. Encode the following binary words into 7-bit even parity Hamming code: (i) 1000 i) 1011 #}lowing ss TRUE/YESION represent lope | anf tg My ‘sa events can be recogni these logics associate Wi Inbinary logic, the event represent logic 0 3.2.1 Principle of Logic Circuits ran aga dines dileentogcl oes, eS erties, Bovkan ls ch ae krownas oil ccai Te tang tem gal onc Both net and oui ae Sa tia eli. Switching ect one ofthe ext xan ce ichingSeuitconissof evOTAZesOUTCe, switches eS a seed sachs represent Boolean variables. ON and OFF ety Hefeped tas ogc 1 and logic 0, whereas close and open states eye {signed as ope Land logic O respectively aig ‘Hau kewsaswitching cil TheswitchesAand Bae connec and the lap ners withthe source. The witches A and B repeses ‘arial andthe lp iste out asiable. Te lamp wil be ON Gee theswiches And Bae oowloranyonetheswtchis closed othe, SL Ce ne ERM ean ea ts Qise L_Asswiteh v eee | Fig. 3.1 Switching circuit Table 3.1(a)_ Operation of circuit Table 3.1(b) Truth table [seach a [viene [nae] [Toa 3 a oven | OFN | OFF . 0 0 oven | cuose | ow ; i i cose | on | ow ; és i ciose_} cuose | ox i : Open = ogi 0, Close = logic 1 ON = ai 1, OFF gio 3.2.2 Boolean Constants, Variables and Function Boolean algebra differs in a major way 3 input/output terminals ofa circuit. The Bogjees VL Present on a wire or at or logic 1. These 0 and 1 are known as Value of variable is either Io ‘Boolean algebras relatively easy war on ateONsans, because of only two values. In Boolean, negative numbers, square 1001S, cube roy are only three basic funetions, that is Boolean Algebra and Loic Gates 439. ‘These basic functions are called logic operations. The cicuits, which perform nese logic operations, are known a gates, The gates can be constructed from diodes, transistors, and resistors connected i such away thatthe cireuitoutputsthe result bfbasic logic operations performed on the inputs, Letus describe and analyse these basic logic operations ‘OR Operation ‘me switching circuit shown in Fig. 3.2 has two switches A and B, which are connected in parallel and the lamp in series with the source. The lamp iseither ON Gr OFF depending on the state of switch A and switch B. Assis A q ae | There are four possible states ofthe switches: (i) BothA and B are open Gi) A sclosed and Bis open. Gii) A is open and B is closed. (iv) Both A and B are closed. ‘When we think logically, keeping basic ideas of electrical circuits in mind, one can conclude that out of four possible combinations, the lamp willbe ON forthe case (i), ii), and (iv) and it will be OFF for case (i). In other words, the lamp is ON if either switch A or switch B is closed or both are closed. Significance of this logical Statement lis in the words ‘either... or’ which simply represents ‘OR® operation withthe symbol +”. The Boolean expression for this switching circuits. AORB A+B “The operation of the switching circuit shown in Fig. 3.2 is summarized in Tables 3.2 (a) and (b). BL) Table 3.2(a) Operation of circuit Table 3.206) Truth table ‘Switch A_| Switch B | LAMP me ‘OPEN | OPEN | OFF ° ° 0 open | cose | on 0 1 1 ciost | open | oN 1 ° 1 cuose_| cuose | oN fs 1 1 (pen 0, Closed = 1, ON =1, OFF =0. x AND Operation Inthe switching circuit shown in Fig. 3.2 the switches were arranged in parallel, ‘whereas in the switching circuit of Fig. 3.3, they are arranged in series.492 Digital Hectronics sey . mea i Fig. 3.3 Switching circuit for AND logic ntsc gram, amp wilde ON 001 bh ey closed, otherwise the lamp will be OFF. This logic is known as AND jog: My Nae eee peonexesson fr AND operant mt Yeap 03 ‘The behaviour of AND operations summarized in Tables 3.3) ang, , Table 3.3(a) Operation of circuit Table 3.306) _ Truth table ‘Switch A_| Switch B | LAMP. A cap ‘OPEN | OPEN | OFF 0 ° 7 oven | ciose | oFF 0 1 ¢ ctose | open | om 1 0 é ctose_| close | ON 1 af Open =0, Cloed= 1, ON= 1, OFF =0 NOT Operation ‘The switching circuit shown in Fig. 34 has one switch and a lamp. Whenever switch is open, the lamp is ON; and when the switch is closed, the lamp is OF because the current always passes through low resistance path. This operation Known as NOT operation. As per standard notations, output Ys not equal tings ‘A. This means that Vis equal to the complement of A. This can be expressed fed Gy) ‘The operation of the circuit shown in Fig. 34 is summarized in Tables 3:4 and 3.4(b) Table 3.4(a) Operation of circut (Switch a] Lamp wii OPEN | ON ciose |_oFF Table 3.4(6) Truth table al A_ | ¥ea 0 1 o 1 Fis. 3.4 switching circuit for open = 0, Closed = 1, ON = 1, OFF =0 NOT logic A Boolean Algebra and Logic Gates 439) 43.2.3 Basic Laws of Boolean Algebra “The basic Inws of Boolean algebra are given a: () AtO=A ow Gari 63) (ii) AtA=A oo) en G8) 69) 6.10) (iti) AA =0 Gan) In Boolean algebra, the value of a vasibleis either logic 1 or logic . proofs of Basic Laws of Boolean Algebra Gi) A¥1=7 Oral 14t=1 Hence,A+1=1 Hence, A.0=0 (ili) Av A =? Hence, A.1=A Hence, A. A 3.2.4 Boolean Theorems Boolean algebra can be used to analyse a logic circuit and express its operations ‘mathematically. It plays an important role in digital system design. Boolean theorems help us minimize the Boolean equations. The basic Boolean theoremsare listed below. They are also known as single variable Boolean theorems cor basic Boolean laws. Law LA+0=A Law 5:4-0= Law2:A+ Law6:4 ¥1=A Law3A+A=A — Law7:AvAsA Law4:A+ A Law8:A. A =0 Boolean multivariable theorems involve more than one variable. Boolean algebra supports the basic laws of ordinary algebra such as: (1) Commutative law, (i) Associative law, and (iii) Distributive law.4 ectronics 4 “ommutative Law Fee a spat bcerkisi bo rctien Ga oman m0 Law9:A+ +A Pew ited:A “Associative Law ssc hw seta the aouping of Variables in AND o, op & doesnt affect the esl Law I:A+(B+O=(4+B)+C Law 12:A+(B-Q=(A+B)+C Distributive Law Distributive law tates that muplying term-by-term in just the same We "ya inary algebra can expand an expression. Lay 13:4-(B+C)=A-B+A.C Law Ids(A+8)-(C+D)=AC+AD + BC + BD Law IS:AB+AC=A- (B40) 135 0 (AA =a) q 4 (142-0 Gia amin =(A+B\A+ A) _ AA+AA +AB+ AB A+0+AB+ AB Oy Gn (AR = and AA=A) Example 3.1 Prove the following Boolean theorems: oy ne ane aad (@) AFBC=(A+B)(A+Q) () AB+AB= eo () A+B)(A+ B)=A Aa i AB sa 3 © a @ A+ Ape eh Oa A Data + AB=(A+B) () AB+AC+BC=AB+ AC © AA +e)=4B Soltion @) AtBC=Us A406) (2 B+ B =1) [A+B | 4sC] Atac (A+ BYA+O0 | ane e 0 sPohsrail” 0 @) A+B A+ B)=A 3 F aa 7 7 (A+B\A+ B)=AA+AB +AB+BB ees! 7 A+AB +AB+0 _ igs 1 A(L+ B)+AB CURR SS ie feaaiie 1 A+AB Li | 4 1 jl A(+B) +B=1) a ih =RHS. e re i () AB+AC=A+OG +R _ + (A+O(A+B)=AA + AC+AB+BC 0+ AC+AB+BC AC+AB+BC+1mnie 2 aB+ AC+BC(A+ A) p+ AC+aac+ ABC ascarid AB+ AC us aa hts: {A,B C,D)=ABD+ABD Soltin Y=ABD+ABD WA,B,C,D)=AB\D + D) =AB-1 B Example 3.3. Simply the following Boolean equations () MAB. C)=aBC AB +4Be Gi) A,B,C, D)=ACD+ ABCD Solution @ 14.3.0) =ABIC+ 0) Je HABA TB © %A.8,6D)=AcDsapey = CDi sm) Wehave seen that 4.475 Fax. ABCD) =Coasg \CD+.BcD oolean Algebia and Logie Gates 41972 Example 3.4 Simplify the following Boolean equations C+aae ABCD +4 E+ABe Cus (since 1+B=1) Gi) Given Boolean expressions BD (incec+ C=1) 3.3 OVERVIEW OF LOGIC CIRCUIT Logie Gates Logie gate is digital circuit. Ithas one or more inputs and only one output. The inpu(s) andthe output of agate is logic | orlogicO- Here the word ‘logic’ is used because the values of I and O are not fixed. The gates, which perform logical OR, AND and NOT operations are known as basi gates. Any Boolean expression can be realized using these gates. Truth Table Atruth able is ameans to describe how the output of alogiceireuit dependson the logic level present atthe inputs). The table lists all possible combinations of logic levels present a the inputs) along with the corresponding output. There are four entries for the two-inputs truth table, eight entries fora three-inputs truth table, and o on. The number of input combinations will be equal to 2 for an N-input truth table The list ofall possible input combinations follows the binary counting Types of Gates Listed below are the different types of gates: 1. ANDgate 2. OR gate 3. NOT gate 4, NAND gate 5. NOR gate 6. EX-OR gate 7. EX-NOR gateLe Sg en ary of logic gates as sone tocando ster Boolean - : ; rien Seca es Ces 198 expression sookean Expression for Logic Circuits | expression _| any logic eieult, no mater how complex itis, can be deseribed using Boolean -Avyessions. The gates are the basic building blocks ofthe digital systems Examples 1. Consider the logic circuit shown in Fig. 3.5. ‘Thecircuitconsists oftwo AND gates, ‘one OR gate, and the inputs to the OR fzte are the outputs of AND gate, and ‘AND gate. Since the inputs of AND. gate, are A and B, the output will be ‘A«B,andsince the inputsof AND gate; fare Cand D, the output will be C+D. Fig. 3.5. Logic ciruit ‘The output of OR gate is YA, B, C, D)=AB+ CD 2, Consider the logic circuit shown in Fig. 3.6. “Thecircuitconsists of woOR gates, one AND gate, and the inputs to AND gate 4 eS peaupaiet Ol greg Sieedanl Bare the inputs to OR gate), the output eS a oatbed eBiandsine Contacte °—)3>—S 0) lapis DOR gate, be output willbe C snp theeutpitef AND els (A,B, 36 Lonic cru Eye +B). (C+D), 4. Consider tbe topic ot shi in 2 ‘The cleat consists of an AND tnd u NOT gale, Wheaover a NOT gate is po ee A[B teas ste daca) é a [a reat NOT ae ate NC expressions simply equal tothe input "Fig 3.7 Logie circuit yor of1} 0 expression with a bar over it. 3 f ‘The output of AND gate is A « B, and. the output ofthe given logic diagram is ‘The operation of logic circuits is defined by B diagram can be implemented directly from the:eb SO 8g plemented FIE3:9 Implemenya. canbe imply an Booleanexprean Oy nga AND aston it 3.9 s AB+A anexpression Y=! ins three terms (AB. A meds ¥,=AB, ye isshown in Fig. 3.10, "Ty Boole Implement se Be 1 conti Tus exes ogee TH Joga ig ipsa Soe ees —_ = —_ —y tee eee = ABC} fa oa : plementation ofthe Boolean 3.10 I orate Fe eresion Y= AB + AC + ABC 3.4 DeMORGAN'S THEOREMS DeMorgan contributed te wo mest important theorems of Boolean algebra, Thy Deseret nce th Deora’ ist orem states tha he complement of sum of digital sign qi profits complet ie FBeCHAN =A B.C WN oy nother words whenthe ORing ofthe variablesis inverted, itis same as inventing ach varabeindviduallyandhen ANDing these inverted variables. Fig. 3:11)_ Implementation of DeMorgan's first theorem ‘Thesmallcitcleatthe inpatsof : i 3 fan hen gen AND go nett input signals DeMorgan's second theorem sates that the, ‘signal is equal tothe sum ois complement, ‘complement of a product of digit! ROWE, oy In other words, when he cach variable individually Rosle Algebra and Look Gates Nat = - p> Fig. 3.1116) Implementation of DeMorgan's second theorem Example 3.5 Simplify the expression G+O-+D) MA, B, C.D). Solution ‘Given Boolean expressionis WA. B,C,D)=A+0)-(B4D) Using DeMorgan'stheore YA, B, C, D)=(A+C)+(B4D) G.0)+@.d) (A.0) +B.) =A.T +B. Example 3.6 Simplify the Boolean expression: YA, B)=(A+B) Solution Given Boolean expressions. 3.5 STANDARD REPRESENTATION FOR LOGICAL FUNCTIONS Boolean expressions are also known as logic expressions. Logical functions are expressed in terms of logical variables. The value assumed by logical variables is inbinary form. The logical functions can be represented in two forms, viz. (i) Sum of products form (ii), Product of sums form 3.5.1 Sum of Products (SOP) Insum: ‘of products form, the Boolean expressions are defined by the sum of product terms. This form consists of two or ‘more AND terms that are ORed together, Each AND term consists of one or more variables appearing in either complemented or uncomplemented form.ores eapaBC + input B. The first ANI t 2 ete nan tera sai mc OY N (POS) juct of Sums ( aes 3.5.2 Prod ee Bann xeon a fined BY the prog nett oes er cor ta 0 OR LE, Which ht shen fof one oF more Variables in coy terms TH Oke cami maa fs leat fom For esa . reek Ti ft OF am contin ry 8 amon he varnles (A+B co spon : eh ei goer eB 346 MINTERM AND MAXTERM sron(421)sinte form ofsum of products, and the output is a fune eircom hme viable each termin the sum of products form contains all the variables (lie seatbeespesnshna stondard sin of products form or canonical sn products foranexchindsdualtem nstandard sum of products formiscay sinter. “The SOP fem cane conerdo standard SOP form by ANDing the tess theexpression withthe tems frmed by ORing the variables which are not peer in that erm athe complements. For example, YA,B,C)=AB+ABC +B G3] The first term of (3.23)hastwovaiales andthe third term has one vat abs eft. val Cismising:in the third term, variables Aa missing an hee gt te standard SOP form, multiply the first tem! (C+ C) andthe hind emby (A 2) (CG), ee i YA,B,O) NCSO)+48C+ Bus Zy(047) SOME ABC SABC ABT + Theta ninemsn ee? ARCH =m Aaya ABC(100)=m, TBogg a a BC+aBe BC ABC+T BC+ om ABC(01) ABC (000) =m Boolean Algebra and Logic Gates 44 Equation (3.24) can be written asa sum of minterms, as follows: YA. B, C= Dm, 1, 4,5, 6,7) each term ofthe producto sums contains al the variables, then the expression jsknown as standard product of sumsformor canonical product ofsumsform, a3 ‘och individual term inthe standard product of sun form is called as mater. “The POS form can be converted to standard POS by ORing the terms in the expression with te terms formed by ANDing the variables which are not present in that term and their complements. For example, YA, B, C)=(A+ BYA+B+ C) ‘The firs erm ofthe above equation has two variables, variable C is missing. and hence to get the standard POS, the term (C) inthe first term must be ORed. YA,B,0)=(A+B+C0)-A+8+ 0) (A+B Clas B+ TyA4B+ 0) 25) “The otal maxterms are thee, which ae (A+ B +0010) = (A+B +Tyo11) =m, (4+B+T)(001) =m, Equation (3.25) can be written as a product of maxterms, as follows: YA, B, ©) =TIM(, 2,3) For SOP, the uncomplemented variable corresponds to logic 1 and the ‘complemented variable corresponds o logic 0. ForPOS, the uncomplemented variable corresponds to logic 0 and the complemented variable corresponds to logic 1. The ‘minterm and maxterm for three variables are given in Table 3.6, Table 3.6 Minterm and maxterm for three variables a seo : of ol o 35C A+B+C=My Csaba ABC=m AxBsC =M, cl ses at a A+B+C =m, eae ae ab AtBsE om, | De | cs [ean ABC =m, AABEC=My 1 uaa ABC=ms — A+B+T = Ms sia (ett ABC =m ete de eae ABC =m cepiers for he fancton Beoiesn Agta and Lone Stes _ 7 te 2 sample ape “Tis equation can be converted nto standard POS by ORtng the first erm by (c@>), second term by (A), and thied term by (BB). a Zsad a.074B (A+ B4CKA+B+TYA4B+CXA+B4C) averted into standard SOP form by muy, a mine #0) (A+B+O1A+B +0) A+B + O)A+B+C)(T+B+0)A+B +O, Hach term of the standard POS is called as maxterm, ig +B (A+B401000)=My (A B4ZYOO1)= Mh = ABC(00) =m 2 a agcqon=m 450 GrarTwoy=M, A B+ CHOI) = Me ‘ABcao) =m, ABC(O10) =m “The expression in terms of maxterms can be written as ners of miners, the expresson Will YA, B, ©)=TIMO,1,2,5) 6) TA O=T0 245 3.7 SIMPLIFICATION OF BOOLEAN EXPRESSION 3 flloving Boolean fnetion into standard Sop gy ‘ample 3.8 Convert expres tin terms of miners. 1U,B.O=AB+AC +BC ‘The design of digital system is nothing but to determine the Boolean expression from the given information and to implement the Boolean expressions by using suitable digital components [.e. gates and flip-flops]. To reduce the requirements ‘ofhardware, itis necessary to simplify the Boolean expressions. Boolean expressions can be simplified using (i) Algebraic simplification, (Gi) Karnaugh map method, or (iii) Quine-MeCluskey method. Solution Given equations 14,8, =4B+AC +BC ‘Thisequion an cone ito stndard SOP by multiplying thefstey + (C+ ©), second em by (B+ B), and the third term by (A + A), MA,B,©) =ABIC+C)+AC(B + B)+ BCA + A) =ABC+ABC +ABC +ABC +ABC+ ABC =ABC+ABT +ABC + ABC ach tem of the standard SOP canbe represented by a minterm. 3.7.1 Algebraic Method Algebraic method is one ofthe simplest methods to simplify the Boolean expression. Inthis method, Boolean theorems are used o simplify the expression. The drawback. ofthis methodisthatthere sno way to distinguish whether the simplified expression isin ts simplest form or it canbe simplified further. For example, ‘Y(A, B,C) =AB+AB (A + C) ABCA) =m, ABT(110) = mg ABC(010) =m, (since A« A=0) be written as A,B, 0 =5n0,4,6,2) Frample 3.9 Convert the Example 3.10 Simplify the logic circuit shown in Fig. 3.12. cxpres hit ere of mani movin Boolean function into standard POS a! s WA,B.O)= (A+ ByB 42 5 Solton eo 4 Given equation is a YA, B.O)=(A +.) 4 B Fig. 3.12 Logic circuitpital Best us_Beln Be a Solution given logic ercuitis “The expression forthe yerthets f Solution a ABC, Ys=AB “Ouiput Ysa summation of miaterms mma. ms nd me. yoAB+ABC+AB Be m= 010-4 BC mp=100 = ABE me=l10 = ABE 2AB+ABC ‘Boolean expression in standard SOP form: WA,B, ©) =A BC + ABC +ABC +ane Example 3.11 Simplify te expresion: YA, B,D) = (A + ayy aa J ACE +B) +ACB +B) =A 4AT Solution Given Booleanexpressionis YA, B, D) =(A+B)(A+B+D)D EA +a) =(4+)(AD+8D+DD) in =(4+)(AD+BD) (since DD =o) Example 3.14. Sicaplty te follwing tateevariibls Greene =4A4D +4BD+ ABD + BBD si ee eae : = ABD+ABD+BD (since A = anda Solution | oe eee =BD(A+A)+BD (Output ¥ is a summation of minterms mp, mt, mma, ma, mm ac M- =D +BD (ince A +a=1) =D my= 111 = ABC Erample 312 Sy tefolovng eve expen sng Bi Boolean expression in standard SOP form: : 8 nti i 8,0) =ABC+ABC + ABC +A.BC + ABC. YA, B, C= 3m 0, 1,3,4,7) ae + ABC +ABC + AB Solution =4RC+0+4BC+0)+ABC+0)+A8 Output Visa summation of misters mm, ms, and my. =AB+AB+AB +AB meme my = O11 = Hae 4 2A@+B)+AB +B) me10=ABC melt =agc a Boolean expression in standard SOP form: WA, B,C)eer AaB eC +B+OKR+ B +e) a+ B+oK Rh ie rc. ~ eM cobs BBSCB+AT+ BCT @, 14,8 O- UAT 4 ABeBBHBCHAC HBC, (Aa+a Be m sumac ciphapace ne ores Beto or ABY eh Bi ar, a Far TKATB)+ ACs Tayp vue cyeaedy+ CBK (B+) 4AtCBKA + AC+E astand oo (A+) 1A.B.O= 1A. ae na BO=A+CBKA +E) wangagaakoreeen” Wa,B,20+AC +4 pate 1a,8, =AC +(AFDCB WA,B.O= AC+CB 3.7.2 Karnaugh Map Simplification tied: "pete implication mead sa drawback that teres 0 easy Way ty es ei el enericnin sd fet Ts problem falgebraesimplifation methods overcome in Kamaugh imap Knap) sina, f : enc apical cigs to simply Boolean expressions. It provides a is 0;thetermof group 1 is CD. For group 2, variable Aand variable Bis O or 1s and they are eliminated, Cis 1 ‘and D is 1; the term of group 2 is CD. The simplified ‘equation isthe sum of these two groups, it. Fig. 3.33 Kemapae tele. sn eilone ats ‘Me same logic can be extended to 16, 32, and 64 adjacent Is, The procedure simplify the Boolean expression using K-map is 1 Represent the sum of products expression on a K-map, 2, Form the groups of possible adjacent 1s a8 8,4,2, 1 3, Write the Boolean term of each group, ‘4, Write the simplified expression in sum of products form. { “Fig 3.34 Kimap ‘éxample 3.18 Minimize the following expressions using K-map: (a) YA.B,©)=2n(1,3,5,7) = ABCD +ABCD+ ABCD + ABEp OA Oe oe B DAR c= Em(0, 2, 4,6) A BcD+ABCD+ABCD Bey} MA,B. C= Em00,2, 4,6) ACpe+B)+AC Tenis Solution CODY B)tACHB+B +A CDGB)sreyy | a) WA. B,C)=2m( 3.5.) Aeb+ATD+ Acb+acp si “The representation of SOP by K-map is shown in Fig. 3.36(a). Foic+0)+AD(C+C) eee Y(A,B.O=C =D(A+A)=D es Fig. 3.36(a) YA, B,C) = Em{1, 3, 5,7) ‘hsexpesson canbe directly obtained from K-map by using the fy procedure: = (b) YA, B, C) = Emi(0, 1,4, 5) “The representation of SOP by K-map is shown in Fig. 3.36(b). 1, enfant Is eet valveo the variables associated with thea the varies thos ate Oo wil eliminated. Other variables wl in ANDed frm, In his form, the variable 4p wilbeiauncomplementedformifitis Land cj 00 01 inthe complemented form ifs 0. 00 7 [ Talo 2. Ifthe groups are more than one, then the 4 a epatectorcicn ©! 3.3616) YA, B, C) = Em(0, 1, 4,5) Wiseman Besimpedention 1 © YA, B,C)=Em(0, 2,4, 6) in ct frm sobained by ORi 0 ene ceaheee wyORing | “The representation of SOP by K-map is shown in Fig. 3.36(c). ait loing example, Fig, 3.35 Kan oo _o1_1_0 ager na 1,CisOor 1, Dis0 or 1 and they are elimina 9 YUB.O~ i Ye : meee Intheabove, Fig. 3.360 iA, 8, O - m0, 2, 4, 6) Example 3.19 Minimize the following expressions using K-map: (@) YA, B, C)=Em(0, 1,2, 3,4,5,6.7) int (b) YA, B, C) =Em(0, 2, 4) ci ‘sfoundthaySS™#OUPSOF2 4 and 8 adjacent Is are considered, anety s. pista Bee x sotution (a) YB se K-map epresenaton sh 3,4,5:6-7) 5. cp=3m00. 1s fown in Fig. 3:37(a. YAB.O=1 ig 327 WA @ = Em0, 1,2, 3,4,5,6,7) (ey 1,8, C= 20.2.9) map represen shown i FB: 3. 370), 4 vida, =70+FC ieee Aca Fe 3570) WA 5 “0 = Bmi0,2, 4) srample 320. viinine te folowing expressions wing mar Mey AB, C,D)=Er(0 12,3, 44546, 111510) (0) WA.B,C,D)=2m0, 247,810.12 19) Solution oa heb, C,D)= Bf 1, 23.4 5.6.7, 119 1) se Kamp representation is shown in Fig: 33800, 4+ BCD + BCD + BCD Fig, 3.3810) YA, B,C D) = m0, 1,2,3,4,5, 6,7, 11, 314) ‘The simplified Boolean express is YA,B,C,D)= A +BCD+BCD+BCD (0) YA, B, C,D)=¥m0,2,4,7,8, 10, 12, 13) ‘The K-map representation is shown in Fig. 3.38(b). _ apse ITT er cean Beolean alge and Logie Sates _ | y-CD+BB+ABC+ABCD fig, 33000) YA, B,C, 0) = Emi, 2,4 7,8, 10, 12,73) se simplified Boolean expressions WA, B, €,D) ED +BB +ABbC + ABCD rample 2.21. Minimize te following log fnetion using Kamae "1B, C,D)= S(O, 1.2.3, 5.7.89, 1a 14) and implement it using logic BES Solution The logical function is YA, B,C, D) =2m(0, 192.3, 5:728.9 11,14) rhe K-map representation is shown in Fig. 339, ‘The simplified Boolean expression is YA,B,C.D)= 4B + AD+BC+BD+ABCD -thi expression canbe implemented using AND, OR, and NOT gs Fig3.29 YA,B,C,D) = Zm(0,1,2,3,5,7,8:9: 1,14) eee oe OR Fig 3.40. Implementation of WA, B, CD) ~ Asample 3.22 Minimize te followin 198 fonction wy ra sing Ky A,B,C, D)= 20. 1.2. " and implement it using logic gates. 4.7.8.9, 10,11, 12,14) Solution ‘he logical fonetion is A.B. C.D) = 3m, 23.4.7, 8,9: 10,11 12,14 tue K-map presentation is shown in Fig. 3.41 Ot aE ofall uw 7 a wu Fig341 A,B,C, D) = 200, 1,2,3, 4,7, 8, 9, 10,17, 12,14) D+AcD+4ap ‘Simplified Boolean expression is YA.B,C,D)= ACD+AD + D +B “This expression can be implemented using AND, OR, and NOT gates go Fig 3.42. Implementation of 1A, B,C, 0) = B + TD + ACD + ABD Example 3.23 Simplify the following Boolean expressions: (a) YA.B, C, D)= Dn, 2,5,6,8,9) (b) YA. B,C, D)=Bn(0, 1,2,3,4,5,6, 11) , Solution (a) The Booleanexpressionis YA, B, C, D)=Em1,2, 5,6,8,9) “The K-map representation is shown i Fig. 3.43(a). a " oN wo ot h YAB.CD)= AEDs RCD 4ABT 1 a Fig 3.43) Boolean Alga and Log Gates SN6S. (py The Boolean expressionis WA.B,C,D)=Em(0,1,2.34,5,6 10) - « K-map representation is shown in 3.4300). -The simplified Boolean expression is ABCD) AB+A D+BeD Fig 3.4300) xample 3.24 Minimize the following Boolean expressions SN K-map: B+CB+C () MA,B,C,D)=ABE +BCD+BCD Solution Sem: fhe given SOP isnot ina standard Form should be converted into standard SOP. sep 2: Weite the expression in terms of intr, ‘ep 3 Represent the expression by K-maP. Sica: Form the groups of posible adjacent 1s a8 8,442: Sep 5s Writ the Boolean term for e8ch E100P sr Write the simplified expression n sum of prot forms (a) YA,B,C)=AB + CB +C see ipa hrce-variable Boolean expression Variable Ci missing 8 fist term, Ais missing in the second term, A and B are ‘missing in the third raserad the expression is notin a standard form ANDing the fis \e5T ‘with (C +0), second term with (A +A), and third term with +”) (+B) the standard sum of products form is obtained (A, B, C= AB(C +E) + CBA +B) + CUA + AB +B)) =ABC+ABC+ABC+A C+ ABC+ABC+A BC+A BC =ABC4+ABC +ABC+A BC+A BC Inminterms, the Boolean expression can be written YA, B,C) = Bm(7, 6, 5,153) “The K-map representation is shown in Fig. 3.44(@).Te simplified Boolean xeon 1A, B= C442 ¢.pyeae +8CD+BCD able enenereson sem iy sia en, Assn the cond ee | ‘standard form, a Dest en tn sn 0 ANDi get a geseoatemih t+ 3th nar sum of pods frm Oba ‘ pO(D+ D)+BCDA+A)+ BCD (A 3, ‘Thisisal is missing in WA.B.CD) = } o=nM0.3,5.7) shown in Fig 3.54 (2). ee menace: ?/%7) ii pootean expressions A,B, C)= C (oy The Booka xpesionis A.B, )=11M 0. 1,4,5) is shown in Fig. 3.54 (b). oo i 3546) YA, 8,0) ~ FIMO, 1,4, 5) “Te simpliied Boolean expression is (A,B, C) = B (A, B,C) =TIM(,2, 4,6) en a an ta Ger, Fig. 355) YA, 8, = TIM, 1,2,3,4,5,6,7) “the simplified Boolean expression is YA, B,C) =0 {py The Boolean expressions YA, B,C) =TIMO, 24,5) ‘The K-map representation is shown in Fig. 3.55(b). 4B too ovo Fig. 35506) YA, B, © = IMO, 2, 4,5) “the simplified Boolean expression is ¥(A, B, ©) =(A+ €)-( A+B) Example 3.30 Rede the following fonetion using K-map technique, (A, B, C, D)=TIM(O, 2,8, 9, 12,13, 15) Solution ‘The Boolean expression is ¥ (A, B, C, D)=TIM(O, 2, 8,9, 12, 13,15) “The K-map representation is shown in Fig. 3.56. 4B. @ 00] o oim sions shown in Fig. 3.57. & ‘The K-map representa __Bonean high and Logic Gates 479 ‘The simplified Boolean expressions YA,B.CD) A+B +C4DVA+ BVA Dyas) example 3.33. Simplify he following Boolean expressions: (a) WA. B, C.D) =T1M (1, 2, 5,6,8,9, 10, 11,15) {by YALB.C,D)= TIM, 1,2,3,5.6,7,12, 14) solution wad A = 1IMO, 1, 2, 3,8, 9, 10,11, 12, 13) (a) The Boolean expression is YA, B, C, D)=TLM(1, 2,5, 6,89, 15) ne 2 ‘The K-map representation is showin in Fig, 3.59(0, T+0, as rhe simplied Boolean expressions WA. B,C,D)=(4 + OB a Seen Example 3.32. Simplify he following Boolean expressions aS (a) HA, B, C.D)= TIM, 2,5,6,8, 9515) ; () MAB, C.D) =TIMO, 1,2, 3,5: 6,75 12) “| Solution a (a) The Boolean expression is WA, B,C, D) = TIM(L, 2, 5,6, 8,9, 15) “The K-map representation is shown in Fig. 3.58(). Fig. 35%) Y\A, B,C, D) = TIMA, 2,5, 6,8, 9, 10, 11,15) Fo 1 10 “The simplified Boolean expression is tw a ) YA, B,C,D)=(B+ AYA +C + DYA+ C +D\A+C+ D) (b) The Boolean expression is Y(A, B, C, D) =TIM(, 1,2, 3,5.6,7, 12, 14) ‘The K-map representation is shown in Fig, 3.59(b). 4B co tt Fig. 358 YA, 8,C,D) = TIMI, 2,5, 6,8, 9, 15) ; ‘The simplified Boolean expression is - YA.B.C.D)=(4 4+B40(A +B 40 + BAF +D)(A+C+D) ie 0 (b) The Boolean expression is WA B,C, D)=TIM(O, 1,2, 3, 5, 6.7, 12) i ‘The K-map representation is shovin in Fig, 3.58(b). Fig. 3.596) YIA, B, C, D) = TIMO, 1, 2,3, 5,6, 7,12, 14) oy ol 0 ‘The simplified Boolean expression is WA, B,C,D)=(A +B +DXA+BYA+ DA+C) Example 3.34 Minimize the following Boolean expressions using K-map: (@) WA, B,C, D)=(A+B+ CA +B+D) (b) WA, B,C,D)=(A+B + D(A +B+D)etoes_—_—— —— ‘vasa all o_o ae Boolean Algebra and y Se sotto ous snoinstanda 70s Ec ean? —_ 3c given roe i“ +B+D+ OTs Bap sce sep |: wigan FU is eg A+B +D+CCKA+B 4D +0) pe peexpesin infers of MANS =(A+B+C+DYA+B 47+ D) ‘ep 2: Waite ion by K-map. Ae. CoB date cae express G+ Be CsDyas Bae 3: Represent ile adjacent O5 28 8, 4,2, and 1 oo ae Forme ours POSS cs ret navn ieee 3B oo a 13,15) te Boolean rxm fore ‘The K-map representation is shown in Fig. 361 sp 5 Wie expression in product Of mS form, 48 ‘se Wee si oto o_o o A +B+D) C.D)=(A+B+ OH I ee expen 8 ot sy four rable Dismising inthe ist term, Cis mssingn he expression snotinstadard frm. ORing the first tnd the second tem with C, the cobained 14,8, C,D)=(A+B+C+DDXA+B4+D+CC) =(A+B+C+DYA+B+C+ D) (F+B+D+0(A+B+D+T) TIMO, 1, 8, 10) This canbe written as VA, B,C ‘The K-map representation is shown in Fig. 3.60(a), 48 Gow o oon oO. " no ig Fig. 3.60) 1A, 8, C, D) = TIMO, 1, 8, 10) ‘The simplified Boolean expression is Y(A,B,C,D)=(A+B+C\(A +1 (©) MA,B,C,D)=(44B + DA +B+D) {iss fou-varable Boolean expressonin product of sums form. I TT - andar product of sums fom Fig. 3.61 YIA, B, C, D) = TIMG, 7, 13, 15) ‘The simplified Boolean expressionis Y(A, B, C,D)=(B + D)(A +B +C) Example 3.35 Minimize the following expressions using K-maps. (@) YA.B, C, D)=TIM(L, 2,3, 5, 6,7, 9, 10, 11, 13,14, 15) (b) YA, B,C, D) = IIMA, 4, 6,9, 10, 11, 14, 15) (© YA,B, CD) =TIMQ, 7,8, 9, 10, 12) Solution {a) Given Boolean expressionis___Bovian Alpe nd Logie Gos gp ‘Towritethe simplified expression in sumof products frm, we haveto frm {roups of adjacent Is as shown in Fig 3.63(5. or 4a ora oi: Fy ig. 3.6200) 1B, Gr ‘Thesimplfed Boolean expres ° seers Fig. 3.6306) YIA, B, C,D) = Emit, 4, 6,9, 10,11, 14,15) “The Komap representation i 48 ool oy ‘The simplified Boolean expression is YA, B,C,D)=AC+ ABD + BED (b) Towrite the simplified expression in product of sums form, wehaveto form _proups of Os as shown in Fig. 3.63(0). ‘The simplified Boolean expression is VA,B.CD)=(H +B + C\B+C+DXA +B +C\A+B +) fig 362(0 A,B, CD) ~ TIME, 7, 8, 9, 10,12) iii Simplified Boolean expression is e (7 +Bs0(4 +C+D\B+T +DNA+B + T 4D) i Example 3.36 Write down te simplified Boolean expression in 3) sam | u prodvets form and (b)produts of sums form for: | ia () WA,B,C,D)=Bn(1, 4, 6,9, 10, 11, 14, 15) | Fig. 3.680) YA, B, C, D) = Emit, 4, 6,9, 10,11, 14, 15) Gi) 14.8, C.D) =TIMO, 35, 6,7,9, 10,11, 12, 13,15) Selation (i) Given Booleanexpression’s (i) Given Boolean expression is YA, B, C, D) = TIM(, 1, 3, 5,6, 7,9, 10, 11, 12, 13, 15) nea Zat 69:10 11419) “The K-map representation forthe given functions shown in Fig, 3.64 ( ‘K-map representation is shown in Fig, 3.63(a). The cells that do nt ‘The cells that do not contain 0 are assumed to be 1. contain 1 are assumed to be 0. “a oy on _ 10 w|o[ije]o oft fofola ¥-DG+B+ a+ B+ it pl pian; UrBeOG+B+ ofela lata Fis. 3.631) 14, 8 "8.6 D) ~ Emit, 4, 6,9, 10, 11, 14, 15)(2) Tove thesimpliedexpesionin sumo rogutor, yay groups of adjacent sas shown in Fig. 3.68(b). mo 4 [a oo Fig. 3.640) A,B,C D) = EMO, 1, 3,5,6,7,9, 10,11, 12,45 15 The simplified Boolean expression is ED +ABCD + ABC WAAC + Het 5 (b) Towrtethesimplifiedexpression in product of sums form, Wea groups of Osa shown in Fig. 3.64(0). Ne tOf Fig. 3.6410) ‘The simplified Boolean expression is YAB.CD)=(A +B + OA +B+ CXA+B + CMA+B+OD 3.10 DON'T-CARE CONDITION "ote ofmiterms and don’ 2a 2a oe : pena 2, tnterms of maxterms and don't-care conditions YA. B, C.D)=TTMO, 4, 5,14, 15) «att, 2,7) Example 3.37 Simplify the following Boolean expressions (@) Y=Zin(l, 3,7, 1h 15) +0, 2,5) (o) Y=TIMG, 5.6.7.8, 12) aC, 2,3,9, 11,14) Solution Ya) Given Boolean functions WA, B, C,D)=Em(1,3,7, 11, 15) +d(0,2,5) “The function is defined in terms of minterms and don’teare conditions K-map representation ofthe given function is shown in the Fig. 3.65(a), “The simplified Boolean expression is A,B, C,D)=CD+ 2B Fig. 3.6500) (b) Given Boolean function is YA, B, C, D) = TIM, 5,6, 7,8, 12)+ d(1,2,3,9, 11, 14) ‘The function is defined in terms of maxterms and dont-care conditions. ‘K-map representation of the given function is shown in Fig. 3.6500). ‘The simplified Boolean expression is, YA,B,C,D)=(A+ BYR +C+D) From the above problem, it is clear that x ‘mark in a cell may be assumed to be 1 or 0 if itis necessary to form a larger group of adjacent ones or zeros, otherwise it is neglected.180 Digital Electronics The function is define in terms of interns and don... map representation ofthe give ction is shown np ny in ‘The simplified Boolean expression is 44 YA, B,C, D)= BD+ CD+ABC +AD Fig. 3.6600) (b) Given Boolean functions YA, B, C, D) = TIM(, 2,3,8, 9, 10, 11, 14) + d(7, 15) The Function is defined in terms of maxterms and don’t-care cond K-map representation ofthe given function is shown in Fig. 3,66(6) 2 oto 10 fy $3) Fig. 3.660) The simplified Boolean expression is YA, B, C.D) A+BXA + T\B4 CxB+ D) Example 3.39. Simplify the following functions: (@) MA, B,C, D)=3m01,3,7) 44 13. Dd, 5) (b) MA.8,G D)=2m,3,7,11,15)40,2.4) Solution (@) The Booteanfnctonis a ra BG P= 300, 1,3.7)4.40,5 rei hs fncon seed interme ot * | * eee ee the given faction iy ie 3.671) expressions A,B,C, D)= 7 +C Eas Beclesn Alga tp) The Boolean function is YA, B, C, D) = El, 3, 7, 11, 15) + 0.2.4) rrhe function is defined in terms of mminterms and don't-care conditions. map representation ofthe given function 3.67(b). The simplified Boolean function is YA,B,C,D)= A B+ CD jg shown in Fi FIVE: AND SIX-VARIABLES K-MAP “The Kemap representation and minimization fot 2 3, and variable functions is The ved in previous sections. Kmap can also be used to simplify the Boolean Srpressions of five and six variables M fve-variable K-map requites ° =32 cells anda six-variable K-map requires pa cells A five-variable K-map is shown in Fig. 3.68. epee: ox’ o_o ‘10 ao | ea nf WEEE oP Fig. 3.68, Fivevarlables Kmap consists of two four-variable K-maps, the variablesare B, C, Dand E. Forthe fist map, A= 0, and forthe second map, A ‘A six-variable K-map is shown in Fig. 3.69. consists of four four-variable K-maps, the variables are C, D, E, and F. For the frst map, A = 0 and B=0% fr the second map, A= | and. =0; for the third map, A =0 and B = 1; and forthe fourth map, A= | and B= 1. Infive- and six-variable K-maps, itis very difficult to identify adjacentcells 10 form the groups, To form the groups of adjacent cells, remember the following points: 1, Two cells are said to be adjacent if they differ by one variable 2. Four cells are said to be adjacent if they differ by two variables. 3. Eight cells are sad to be adjacent if they differ by three variables 4, Sixteen cells are said to be adjacentf they differ by four variables. ‘The same logic ean be extended for groups of 32 and 64 cell.wf | 10] * 3.69 Sixvariables Kmap Example 3.40 Minimize the following Boolean functions using Koma (a) YA,B,C.D.E)= Sm, 16, 17, 18, 19) (b) MA, B,C, D, E)= Bm, 20, 21, 22, 23) Solution (@) Given Boolean function is _Bovlean Algebra and Lose Gates 489) itis afive-varlable Boolean function. Its K-map representations showin ig, 3.6800) rhe simplified Boolean expression is YA, B,C, D,£)=BC Example 3.41. Miimize the following Boolean fwnetons using K-maps (ay A,B, C.Ds E)= Zam(, 1, 5, 6,95 13,14 17,21, 225 25,29). (0) YA, B,C, D, B)=T1MG, 4,7, 1, 15, 19,21, 28,2 28,2939) Solution (@) Given Boolean function is YA, B,C, D, E) = EO, 1, 5, 6,9 13, 14, 17,21, 22,25, 29) iLieafive-variable Boolean function. Its K-map representations shown in ig, 3.650 th BC DB) = E123, 16,17 18,1) a, 0 is afive-varable Boolean function. Its K-map representati A Ar Fig. 3.68(, era eo ww eae Ant 00) a ac | ae ‘DE 10 oro Ww | Fe 260 14.80 basa, 1,2, 3, 16, 17, 18, 19) (b) Given Boolean fun i nC, "ABCD. Ban, . P28 567.20.21.22 25 Fig: 3.691) YA, B,C, D, 6) =Em(0, 1,5, 6,9, 13:14, 17,21, 22,28; 29) ‘The simplified Boolean expression is VA,B, C,D,E)= DE+ ACDE + ABC D +ABCDE (6) Given Boolean funetionis YA, B, C, D, E)=TIMG, 4,7, 11,15, 19, 21,23, 27,285 Itisa five-variable Boolean funtion. ts K-map Fig. 3.69(b). as caoP e690) WA 0,CD,0 =1IMB,4, 711,15, 19,21, 28,27 28 35 yy “The simplified Boolean expression i WU RCD.BAD +EXA +E +EXA +40 DAAC syge Example 3.42. Minimize the following Boolean function. YA,B, C.D, E,F)=Em0, 1,2,3,5,7, 13, 15, 21, 23,29, 31, 37,39 + 31,37, 39,45 41,53, 55, 61, 63) Solution Given Boolean function is YA,B.C,D,E.F)=Em(0,1,2,3,5,7, 13, 15,21,23,29,31 7,13, 15,21, 23,29, 31,37, 47,53, 5,61, 63) fis It is a six-variable Boolean function. Its K-map representati we 1p representation is shownin acl © a polo on a u 0 G @ poo np 6) 0 1 pet u 10 Fig, 370 A505 TMB, 4,7,11,15, 19,21, 23, 27, 28,29, 31) a caemiay mu| tong a 1101 m9 lloiv capa each binary number and prepare the term with che Sie 3 eres 1 and 2 of Table 3.1600) a sup 4 Spl th ave proce for He rest and Tepe Unt no gy ‘iminaton takes place. “ble 3.160) Binary equivalents of groups of minterms with check mas TT __. aeacraiegas Table 3.16(€) Prime implicants selection chart ample 3.44. Simplify the following Boolean expression vsing Quine- Srctiskey method oe ¥(A,B.C.D)= ABC D +ABC D+ ABTD+ABC D+ABC D Solution ‘Given Booleanexpressionis W(A.B.C.D)= ABC D +ABC D +A BCD+ABCD+ABT D 100) 4000) O00) GION 1100) Inminterms, the function canbe written a, YA, B, C, D) = Em, 4, 8, 12,13) ‘ep 1: The given minterms and their binary equivalents are shown in Table 3.172). (Refer columns | and 2 of Table 3.17%(a)). ‘sep 2: Arrangement of minterms according to numberof 1s is shown in Table is aa 3.171. (Refer columns 3 and 4 of Table 3.171). pee cea check mark with check m Table 3.17(@)Minterms in the binary equivalent and groups of minterms ae 10-7 45,12, 13 10 [Minterms [Binary representation 412 1004 im ooor 0001 38 “1017 m 0100 o100v a 101 ae 1000 L000” {ims oy mi 1100 T1007 iis Tor Tow ‘Step 5: The listo prime implicants is shown in Table 3.16 (c), Table 3.16(¢)_ List of prime implicants 45,1213 Str Ske miimum mnt of ries tat must over al te ie prime implicants selection chart is shown in Table 3.16(d)- Step 3: Compare each binary number with every term nthe adjacent next higher category and if they differ by one position, put a check mark. (Refer columns 1 and 2 of Table 3.17(b)). y Step 4: Apply the same procedure for the result and repeat uti ji ‘elimination takes place. (Refer columns 1 and 2 of = ae Table 3.1706). Binary equivalents of groups of minterms with check marksbigtal Beetones _— — 190 is shown in Table 3.17(6) = gp Tet imei j Fable 3.1710) List of prime implicants Binary represent SeROo oleae 100 Loo 110. \— ninimam number of primes that must cover Sep, Set th min selection chat is chown in Tables 4 He pine pict selection charts shown in Table 34g Table 3.1744) Prime implicant selection char 1 42 3 i = (0001) + (100) + (1.00) + (110_) ABCD+BC D +AT D +ABe YA,B, C.D) Example 245. Simplify the following function using, Quine McCay method WA, B,C, D)=TIM(, Solution Given Booleanexpressionis YA, B,C, D)=TTM(L, 4, 6,9, 10, 11, 14, 15) ‘This expression is in masterms. It can be written in minterms as WA, B,C, D)=Emi0, 2,3, 5,7,8, 12, 13) ‘Step 1: The list of given minterms and their binary equivalents are shownit Fig. 3.18(a). (Refer columns 1 and 2 of Table 3.18(a). ‘Sep 2: The arrangement of minterms according to number of 1s is shownit Fig. 3.18. (Refercolumns 3 and 4 of Table 3.18(a)). 9,10, 11, 14, 15) Table 3.18) i be 3.18)" Miter in the binary equivalent and groups of mintems [rena 7 ss, 0000 ™ D010 = ™ oo1L ty ms | o am ms a, 1000 od a 1100 ef ms Lis ™ pees Compare cach binary number with every term in: category and if they differ by one position, p ‘Columms 1 and 2 of Table 3.18(b), 4: Apply the same procedure forthe result and repeat unit no fi elimination takes place, (Refer columns 1 and of Table 3 1b)) sep 3 the adjacentnexthigher ut a check mark, (Refer ste ther Table 3.186) Binary equivalents of groups of minterms with check mas (atnerms | Binary representation | Mincerms | Binary representation oe 00.0 as. 000 Se ial DOr a 00 oT NL 0 37 out 53 -01 13 110. ‘Siep 5: The list of prime implicants is shown in Table 3,18) Table 3.1812) List of pri Prime implicants 0.2 08 23 8,12 37 37 3.13 2B. ‘Step 6: Select the minimum number of primes that must cover all the minterms, ‘The prime implicant selection chart is shown in Table 3.18(4), implicants Table 3.18(4) Prime implicant selection chart YA, B,C, D)=(110_) + (101) +011) =ABC +BCD+ ACD.— $$ a. oi ae 190 sity the following Boolean functio, | ye ne simpli sing 9 5 amie te 8 L __ tose sigan and Losi at 49 sectoskey met Smt, 2,305.9: 1214, 15) + akg, . a a a wp, 4.8) The is of prime implicants shown in Table 3.19, Solio jeanexpression is Gi one a S(t, 2.3.5.9. 12, 14,15) +004, 8, uy are mA ms and don't-care conditiog 3 O01 cep AaB ac eer clunag Sigil v0 | equivalent IN 26 } 010. | 3196). ofthe mintemmsaccording numberof, 100 ‘rangement ofthe mint 18 Yo Number of Ig i 5 don't are conditions; their binary equivale he | rile 3.300 Notes ns nae Siem | s ae car] Biars rere “Finary representation | Minterms | Binary veprerm. 14,15 | 11. es aan m | OOo eel [u9.an__} 04 am 0010 ms ooloy g : nap a. | ae step: Select the minim numberof primes that must cover all the minterms = aon aad tonal The prim implicant seletion chants shown in Table 319 (@). - 1001 ms Table 3.19%4)_Prime implicant slacton m toot * Ma) icant selection chart me aga ‘Prime implicants | my [ma] ms ms [mp [oa] me mrs] na | Pe me iit Lioow ieee 7 : a 0100 viv o 1000 titoy Bl sei) Tie ‘Step 3» Compareeach binary number with every term in the adjacent next category. If they differ by one position, puta check mark. (Refescolay 1 and 2 of Table 3.19(0). Step 4: Apply the same procedure for the result and repeat until no fre ria, 7 elimination akes place. (Refer columns 1 and 2 of Table2.370), sy arr ee Table 3.19(b) Binary equivalents of groups of minterms with check mats f HA, B, (01) + (L11_) + (110) + (0_01) + 01) ‘Minterms | Binary representation | Minterms | Binary represent BD+ABC+ABD +A CD+ABC 3 00.1 Iti important to note that itis not compulsory to include don’ are tems in 15 0-01 the final expression. hg 001 Example 3.47 Simplify the following four-variable Boolean funetion using a pa 1,3,9d11 | Quine-MeCiuskey method. 40 “100 | YA, B,C, D) = Em(1,3,5, 10, 1, 12,13, 14,15) 8,9 00, ; I | Solution ee oie | Given Boolean functions 9.4L 101 q YA, B, C, D) = Em(, 3, 5, 10, 11, 12, 13, 14, 15) pi SIAR | ss 1a a leapia esis z cen: 5 ee 21 Talc a Meg ‘ 3=0011 — 5=0101 i ifort) stenio; 2 eee ninterms according to number of Ae as oa SS Minterms Be 0001 S| __ o | es 1010 mo 1010 [a 1100 mus Torr ee | ia mis oa & sr with every term in the adjacent sep 3: Compare each binary number with every term in the adjacent next “ ategryandifthey diferby one position, puta check mark (et 3.20(b)). ‘Suep 4: Apply the same procedure for the result and repeat until no fu elimination takes place. (Refer Tables 3.20(c) and 3.20(4), Table 3.200) Binary equivalents of groups of minterms with check mis ——_————— asia Alora an oie Gates i ‘The list of second reduction table is shown in Table 3.20(¢), Table 3.20(0) inary equivalents of groups of minterms with cheek marks “interms Binary representation ‘The lst of third reduction table is shown in Table 3.2040, Table 3.2014) Binary equivalents of groups of minterms with check marks Minter Binary representation ae ‘mio Ps Phe is mL joo ma coms ‘These ae the essential smizs mie mis mis 1m rime implicants Siep 5: The list of prime implicants is shown in Table 3.20¢e. Table 3.20(€) List of prime implicants Pras iapiieae GR 3 15 att 5.13 “The prime implicant selection chart is shown in Table 3. Table 3.20(0 rime implicant selection chart 10,11, 14,15) 12.13, 14,15) tis clear from the selection (1,3) and (1, 5) along with (10, 11, 14,1 Itisnotnecessary present in 1,3) and 5 is presen in ¢ YA, B,C, D)= (001 ABSSS in eeceemmemmmmmm SUMMARY 1's fist theorem states tat the comy of its complements, ie, + DeMo cual t the produ WBCr NA A-B.S.N nd theorem states thatthe co + DeMorgan’s second comple Perc regal to de Sam of Hs complemen Te Maer sod tage ats gg Plement of * um og ify the folowing using K-maps and imple 10. Simpl implement it using basic gates ol (fla bs 6.8) = B23, 5, 13, 14) + 9, 10 Ip % (i) NP. O.R, = TMA, 3,8, 10,1213, 14 15) 11, Sip the flowing ang K-meps dpe sng ba sol. (i) fb, B. C.D) = Er, 2, 8,10) 8, 7,6, 11,18) W fA.B,C.D)=CD+BCD+RcD+ ABCD 2, Design 4 4bitpray-to-binry converter us erate = het, AvBsCouN =A4B+C+..4N « each term inthe sum of products cont ns all the varia expen i own asthe standard sum of produce ae gy neath able, Kemp, and logic ee Produc aN 13, Obtain the simplified expressions in prod of suns form ding Kms: + Hea em in te pot oF sums cont ll he arte, DoS EP aan ela iso he amd proc of uso te canoes tn () Fd= RATE ye invite in a tandard product of sums is called ofl i + Different methods are used to simplify Boolean ex m= S| Multiple Choice Questions PTESSions. Thee 1 Algebra simplification es 2. Kamnaugh map method 3. Quine-McCluskey method NEE EXERCISES ——, | Review Questions i Select the correct alternative, 1. The Boolean equation of AND operation i. @ ¥=8 () YeAB © 2. Ina half adder having two inputs A and B and two outputs (S ane © are the sum and carry output bits respectively, the Boolean expression foe and Cin tonne of Aand Bis * ate and prove the Boolean theorems. 2 Winch ude ees Osea ances oe 5 Bonin invoranc of Bolan lets nga sytem 3, For binary tal-subusctor having wo inputs ad he sprain ‘expressions forthe outputs DX=A minus B) and X= ABC + BED + ABC {0 Dasa (®) Express f in standard SOP form. Oe aivalean i) Simplity using K-map, 4, Oe be ee (iii) Realize f using NAND ‘Bales only, Or REDD. 44 6 ttn a oe 4 only; : soolean AP, ORS) = TM, 4,6, 9,10, 11, 14, 15) sae 1. Design and imp) 6 tne 18 equation using Quine-MeCluskey melts '. ‘The minimum numberof NAND gates al tonne 10, 13, 14, 15) expression using K-map and realize ement a bit BCD to Excess-3 code converter sngChapter 4 ComsiNATIONAL_Locic Circun, —— Chapter Outline «bong fate et —s 1 peng of adder and subractr using MSI circus ‘ pesign of BCD adder using 7489 + Suty of ALU 1 ayo pany generator and checker 1 Study of sompaator, multiplexer, and demultiplexer 4.1 INTRODUCTION ‘Geer, digital circuits re divided into two categories: 1, Combinational logic ecu, and ta) 25 -Centanoaltsi ety 499 ‘The steps usd to desi combinational loge cc sing gates are 1. Fromthe tof statements orooleanespesonricy rub ables, determine the numberof input and ouput varahce ee ‘Write dow the expression in the form of um of pedis or peas o 3. Simplify the Boolean expression using K-nap or Quine-MCluskey method 4 Implement the simplified Boolean expresionasng th gi diagram s, most ofthe combinational ies Aaa c sic cteits are available the form of integrated eareuits (JO) ICs of moliplexr demblipener adder ALU. pony generator, comparator and code conveeraresvailabe sno) tosimplfy Boolean expressions to design combination loge cates andthe number of external wiesand connections atealso reduced The eat ofthe ystemimprovesby reducing the numberofexternal wiresandeonnega > 4.2.1 Examples of Combinational Logic Circuits Example 4.1 Design and implement a |-bit compartor using loge gates, Solution ‘The comparator compares the magnitude of input aumbers and checks whether cone input number is greater or less than another input number orboththe woribg areequal. Consider A and B are two I-bitnumbers. Thesetwo ae the input of the comparator and A= B, A> B, and A < B ae the outputs ofthe comparator. The truth table of L-bit comparator is shown in Table 4.1 Table 4.1._Inputs and outputs of {bit comparator Tapas up 2. Segue lege cicut cea ay A B AB Inconbiaol ge cuts ouput a any instant of time depend upny + ings present at ht instant of time. Combinational logic cireuits do na ky 0 at ea ‘meno leet (torag device canbe designed using gates oravalteia 1] hale ges eel ae Astra, ALU compartors, party generator and checker, mulpns 1 eh ae emails encoder, and code converters are the examples of combination’ : “ log ces, Kemaps for A B with inputs and Bare: 42 DESIGN PROCEDURE FOR. COMBINATIONAL x LOGIC CIRCUIT a ‘Thecomt Tetieearooeaatembs implemented using gates or avalbel fleing way (0) byast of tne op Tope cits may be specified in ont (Ara Fig. 4.112) Kmaps for A < B, for = B, and A> B From the K-map, we get Boolean expressions as, @aAc. AB ()(A=B)=AB+AB (@A>B. A@Bening of i comparators shown in Fig. 4,14 ~ Fig. 4.100) Logic diagram of one-bit comparator Example 4.2 Design « combinational logic circuit with four in DU vai that wl produce logic I ouipat when the number of 1s in the inp IS sey Solution LetoscnsiderA B,C, and Dare the four inputs and is the Outpt They table is shown in Table 4.2, 4 Table 4.2 Inputs and outputs of the combinational logic circuit a Combination Loiecieuts nq gram is shown in Fig. 4.2 (b se logic ding iB. 4.2 0b) 4eo2 Hp eae te a —j>—* Fig. 4.208) Logic diagram 4 fxample 4.3. Design a combinational logic circuit with thee input variables that wil produce logic 1 output when more than one input variables ate logic 0, Solution Consider A,B, and Cas input variables and Ys the output variable, Truth able for the given problem is shown in Table 4.3, Supa able 4.3. Inputs and outputs of the rat us combinational logic circuit aj efelo] x ofofolo | 4 As a ofoloti]o | ara telifa} a i ee elec. _ 0 1 o 1 Mier inc: &, 0 L 1 oO 1 ailing aaa! i 1 oh 0 Oe lea ye AB+AC+8O Fig. 4.2 K-map for output Y ree ease res ee Vf 0 | 1 | 0 | gig ay ese roan islet D+AancD + a0 tao) cleo en aie is Ba aK ‘ Jo [ora : +ABCD + A Bep + ABCD Logic diagram is shown in Fig. 43 0). fates oR + ABCD +ABc par ete a haya = CD(AB+ AB) + Gc AB+AB) fe ° ee 7 Sa Keech ebsl 0 i + CD(AB+ AB)+CD(AB+AB) mes te 4 =(A@BXCD +.cD) : a +(CD+CD\(A@B) fae AOBKCOD) +A @B\CO tH ao ek roeae Fig. 4.30) Logic diagramcanperfom various arithmetic operations yg systems an Per persis performed in a simil two binary nu ™ nin of 0 med. Onl FUT CSCS CaN OCCU I chads =O e040 Ade tothe next higher bit addition, st forthe addition of two I-bit numbers ig 4.3.1 Half-Adder "The truthtableofhalf-adderis given in Table 44, where A and B are the inp asumandcary are the outputs. Table 4.4 Truth table for half-adder Inpuis Outputs a_| 8] Sum [Carry ofo]o Ge oles 1 0 1 fo 1 ° ieslicy, o 1 call eda, 8S flay late, Pers iscagy Fis. 44 Logic diagram of half-adder 43.2 Full-Adder Abate prion has two 1-bit inputs and. iene eenetted from ‘Aland B wit Maa derision: § (ayn PS Ci is a carry generated ‘adder, Te 5 (um) and A falar greaty Table 4.4, (carry) are the outputs of 4 3) there is no provision to add a carry whi! ower bit order additions. This limitation oft full-adder is a combinational logi¢ from! the fil ‘Komap for Cag $= ABC y+ ABC +ABCa+AB Cy = C,(A B +AB)+ C,(AB+AB) = C,(A © B) + E_(A@B) = C,(A@B) + Cy(A® B) =C,@A@B B+ ACig + BC Cou “The logic diagram of full-adder using gates is shown in Fig. 45. Fig. 4.5. Logic diagram of full-adder Fulladder using half-adder Afull-adder canbe implemented using twohalf-addersand!an OR gate, The Boolean expressions of half-adder are: S=A@B pape eng } (43) ‘The Boolean expressions of full-adder are: S=C,@AGB And Coy =AB+ACin + BC, | S=Cy@S Coy, =AB + AC y+ BC=AB+ACg (B+ B)+ ABC ( ZAB+ABCa# ABC + ABC, wane G+ GUAB+ AB) (> tei =AB+Cq(A@B) =AB+ CoS (© A@acy ‘The fonic diagram ofall adder using halF-adder is Shown in Fig. 4 fig 46 Logic diagram of flladder sing half adder 4.3.3 N-Bit Parallel Adder Fall adders have provision oad the cary, whichis generated from the lower ‘ugivon In ober words, a flladder adds two I-bit numbers withthe previoy, cary. Henceits possible to construct the N-bit adder using. a set of fall-aders ‘onder toad bit binary numbers, 1 full-adders are required. An N-bit paral drcan be consrcted using N number of full-adders as shown in Fig.47. Bur Avy Bea Ave see Bi A yo hence, itis also knownas parallel! 7er0. The carry output of each addet Combination Lage Crete a tothe carry inputof the nexthigher order adder. Hence, tis lao known, ected jseonne ate adder, The block diagram of N-bit adders shown in Fig. #8 ner propa {fet | ae ee Cua Sus Seo 5% ey By Ay BA By do Fig. 4.9 bit parallel adder [Addition of the LSB bits Ao and Bp produces the carry Cp, which isthe i camry forthe next full-adder. Thiscarry when added tothe bits ofthe second postion (ie Co+ 4; + By) produces a carry into the third position and so on. If t is the propagation delay of full-adder, then the result Sy and Co is obtained after delay of $i and C after a delay of 21, $3 and Cy after a delay of 3, Sand Cyaftera delay of 4, and so on. Hence for an N-bit parallel adder, the total delay time is equal t0 Ni, 43.4 Carry Look-Ahead Adder ‘Theparalleladderhas a larger propagation delay and hence low speed of operation. ‘This imitations overcome in carry look ahead adder. Consider the circuit of full- adder as shown in Fig.4.10. S=A@BOC, Cou = AB + Cig(A ® BY a >? Sum, Where and Bare the presentinputs,C, 2 as Ao 'sthe previous carry, is the sum at aa Output, Cans the present carry at output He 10 ola OF Next input carry.insag onfrrader wecal wie Fort ae coated cinernsofcary rosesteTUNCIONANary gong -Teseeqution Fig canbe waiten 8 527, OCH GG Pr Gt : gat function and G, 8 CARY generate Funtig, whee Py scary Pet From Bs. (4.5) and 7s 724,08) From Bas. (4.6) and (48) GAB Carry output of firs fll-ader (= 0), y= Gat iC where Gy =AyB and Pa =Ao ® Bo Cary output of second stage (i= 1), 626,47. =6,+ Pp+ PoC) (Sbstiuing he Value of Cy omy. = G4 P+ PPC (A; Camry ouput of thin stage (= 2), G+ PC, = G+ PAG + GoP; + PyP\C) (Substituting the value of C; from Eq, (4 = Oy+ GPa + GoP Py + PoP PIC. cr Cary output of fourth tage (i= 3), G=G4P,G, Git PAG + GyP) + GoPiPs +, PoP\P3C 4) ; (Substituting the value of C, from Eq, (415) * BGP, PBs GoPsPaP, PoP, PAPAC ae ‘The expressions in Eqs, cy ‘sing AND and OR gue yi" (10) 4.11), and (4.12) can be implement a e fh Milsiciutisknown as look-ahead carry gee Uses ‘etivehigh carry i i andar tT iP three ative high cary output, Se fonbinstional Logie xcuits Fig. 4.11 Look-ahead carry generator Bs Pats a4 4 4 Fade Yall Fie 4.12 4-bit parallel adder with look-ahead cary generator Here, S\= P,® C,,, Pi=A®B, and G;=A,+B, 1074182 i at re i look-ahead cary generator. I his nine inputs and ive outpus, ine low propagate input signals, four active low generate input signals, active high carry propagate, ‘outputs as shown in Fig. 4.13. oefig 4.13. Functional diagram for 74102 ‘relogicexvesso othe opt ial G=0+ PCa 3 +P + PoP GiP2+ GoPsP2* POPP .Cn ay dis, FGRP + GRP, (ay, = (ny From Bgs. (49) 10 (4.17), itis found that 6: G=G; G+76, a ample 44 Draw and explain the 4-bit parallel adder using 1C 74199 Satin {Tl 82isalok-ahead cary generator. generates cary from the carry geney and cary propagate functions, Cay opiate functions defined as P2495, R=408, =408, Cary generator factions defined as GAs yf) § et ee . Fig. 4.14 Logic diagram of 4-bit adder using 74182 Example 4.5 Draw and explain the 8-bit parallel adder using IC 74189, evi yrs el aa Catt ea rc pm twoICare needed, The carry propagate and carry generate functions are defined as P, =A; ® B,, G,=A,+ By But the inputs of IC 74182 are active low, hence, F=A@B, 4,2 B, = G Letusassame and B aretwo 8-bit inputs. The logic diagram of an8-bitparallel adder using IC 74182 is shown in Fig. 4.15. Hh Mle Bike ay! ey a ma a ou Pl (GM Gh GF Gy Pile chai b 7h (4 Po eG q 0 9 % ky § % § q > Sor elgg! ras Sa een %yas 1741883 scrassiet aay Thee functional diagram of 741.993 4° iy scale TTL neared sh Fig 416 erate adder. I'omtains four ful-addery obit inpats and one input carry. ype dy Ay Ay A pale | Ios tS | ae on 555% Fig 4.16. Functional diagram for 741883 rai 16 Aon By Byte te 40 NPIS. Cay ig ene spre itoupts which represent the sumotig Ft eu input and output its possible to implement the adit mates pear han sng C783 Example 46. implement an §-bitbinary adder using 4-bit adder 7483 or 7428, Solution C7483 or C74043is a 4-hit parallel adder. To add two 8-bit numbers, we nal s Combinational Logie cuts p44 4 Sof wo bioary numbers is pefonmed i a Gail giaaaran a auton of Ma aambers Onl ou aes eat ort int asbencn t fey psiion, thse ae (vith borrow 1) osiecireuitofsubactonoftwo L-bitnumbersis called ashalfsubractr. Tae et which performs the subtraction of two Lbit numbers, taking Te boro ofthe pervious tages clled as ful subtractr 44.1 Half-Subtractor seein Cocoa Se a Theta st numbers. It subtracts B (subtrahend) from A (minuend), It has two se i es a tence a oem A ase arigven ne ee ae tpn ite oad brow (© ee outputs. 4 Table 4.5. Truth table of hal-subtractor ee Fig. 4.18 Block diagram of half-subtractor ‘ousetwolCsof-itadder. Figure. 17 shows the logic diagram of an 8-bit adder a ICTS sing 783 7 0 iit 2 AAD 2, 2, Canaan A ? | | | 0 0 tke bbe UL = epic ex hd D=AB+ AB=(A®B) i Th Gy SS SS C= AB , : i ‘he logic diagram of half-subtractor is shown in Fig. 4.19. ‘i & SSS S AB Fig gay e i Mbitadde using 7493 Resierntrie te 2 anal fcantbits oF the numbers Aad =) > bits ofthe numbers sted asthe input cary 10 of four most significa Fig. 4.19 Logic diagram of half-subtractor-bit inputs and there jg ty ewo T-bit inp here is ng oa : os 0 enerated from lower one P*0% acto maybe BEET ver onder yee a asses which in full ubtractor Te tg hoot gnome nfl bat, Tags sn at as PSION ER ny acct iit end zs ‘Pi is acoA bil Ave % ‘scons isborow 9° Ful babe Cot acer [> elena CA Cy | ntmcer |S te ieee panos he FA 20” Block dag og Be oe eh trace fot tlt sn HE Guy By AgBe)+ Cys (A By + AnB n) =Gp3lAy B+ C pile ® By) A,B) + Cp (Ay By) C184, 8B, =F B+ AGit iG B+ TByt AC The logic diagram of full-subtractor is shown in Fig. 4.21. 6a ay tractor using half subtractor ‘ubtractor canbe implemented using two half-subtractors and an OR gate Combinations Lone Cueuits 949) Tet ea below. Wehave sen ha, fr shal sabato, Dut = An® Bo ee pee 29 re Boolean expressions of fll-sbtacor are Difference =A, ® By ® Cy. Borrow = ByCyit AnCrit A oBy Dut © Cy c Bortow =F yB,+ 7 yCyy+ B,C = A gBy+ Kp (By + By) + Bylo But B pCusBy K jCpt By ByCyr Ball + (Cua) + F pBaCy + BiG A But A pByCy1+ByCu + Cu =1) K But ByByCps + BC tAet A MCAnt By T By + H pByCys+BiCu tnt Bin x A ,Bs(l + Cri) + Cri A Bn + Bey) K By + Cust By) A Bp + Cy A, ) Substituting Cx and Dyy from equations 4.22 and 4.23, Dan =An® By) (4.24) ) Difference B+ B, y Borrow = Cai + Ci D ant ‘The logic diagram of full-subtractor using two half-subtractors is shown in Fig. 4.22. Fig. 4.22. Logic diagram of full-subtractor using half-subtractor 44.3 N-Bit Parallel Subtractor ‘Thefull-subtractorhas provision to subtract the borrow whichis generated from the ails can to eulrtgadt tise DonWonamine Hemet posi rower osubtacta binary eS SNag rsareneeded THe pone gk wee nee um ir ef ul sO 8 Shown ny ly ie tein N aN Sores pa Aya Ba, subtracts i Dea > 5 iq 420. int parle! subractor «is connected t the borrow gut of each subuacto inp cre tet The evs bao or sUBtSEOr Degg 4 Four it ublractor Using Adder ott iis tes he process of subtractions performed by sigh tant in of Bf A is equivalent to the ailing pened, aba svbracton I's complement of 2's compleney ret issed Y’scomplement subtraction ‘The subtraction of B from 4isequivalent to the addition of the 1’s complementat BwoA.ieA-B=A+1'scomplement of. “Tel scmplenetofabinar numberis obtained by subtracting eachbitna, | occonpemetng each bit of th umber. ‘Tounderstnd ths process, consider the following examples. 9-8-1 1001. ¢ Binary for 9 1000 ¢ Binary for 8 1001-1000=1001 41 \000=1001 +1's complement of 1000 1001 4 Binary for 9 +0111 # 1scomplement of 8 Combinational Loge Grits 245) 94 ws 1000 ¢ Binary for 8 1001 #Binary for9 1=1000+1's complement of 1001 1000 #Binary for 1000-100 +0110 ¢1’s complement of T110 ¢1"s complement of 1 2 eee at ser in a ree coat cae angen wh sesh en gate an sin compet nm win abraction wing complement set i att aber 1 Et po mmber ngayon 2 Ali ey ery eee tects hin ing CA ern ind es cmplenct of be -rhe lope diagram of 1's complement 4-bt subtraction is shown in Fig, 4.24. ca Ay AA Ao By By By By 4A fo gina Adder P27 20 |G o Sign 0— Positive 1 Negative! Fig. 4.24 Logic diagram of 1's complement 4-bit subtraction Here, four NOT gates are used to find the I’s complement of subtrahend (B).A 4-bitbinary adder (1) adds the 4-bit number A and the ‘L’scomplementof the 4-bit umber B with the initial earry zero. . Four Ex-OR gates are used to find the 1's complement ofthe result, when cary isnot generated The second 4-bit binary adder (2 is used toad the end- around ‘ary, when carry is generated. arom aNite no z , subtraction , a tis equivalent to the addition of 2, rn of BHO , s sre sueraction 75 complement of 2 mae 2s ied by aig | tthe, = ‘complement of er the following examples. "Pt othe Poses “aa ae nic : vind 1000 ea ‘Binary for? ‘shag Soo. Bias fr 8 ita ee toon scomplement of 8 0110 eae git es : 2 _ i ‘ere oor-1000=1001+ <3 ommplement of 8 comple na 1000 Mor 1 +011 +1000 sont FOI Discard the cary, and 1 eae > gee postive res cory isn 27a form. letey 0000 + 1'scomplene be sserataag TDOOT ¢ 2's complemen oftitt tis observed that, after the addition, if canys) correct result i obtained by discarding the ay ative, and it is in 2°s complement form, From the above examples it then the results positive; andthe it ear) i thn the result is neg Algorithm of binary subtraction using 2's complement 1. Find te 2's complement of subtrahend 2. Add the two numbers using binary addition, + Check he carry. Ifcaryis generated, the correct positive results bi by discarding the carry; otherwise the result is negative, jitisin 2’ scompleat form, the correct result is obtained by taking the 2s ‘complement intermediate result, ‘The logic diagram of 2's complement 4-bit subtraction is shown in Fig45. Here, four NOT gates are used to find the 1s complement of subtrahend BS Gpscomnected to Voc toad tothe I’s complement to get the 2's eomplemst of sbtrahend (B), ‘The4-bitbinary adder (1) adds the 4-bit number A and the 2's complenet ‘scomplement of +1) Four Ex-OR gatesare used to find the I'S of the result, whenever carry is not generated. The cond bt binary adder (2) ad the esl of adder 1 andthe uh Ex-OR; it SOR ates withcary 1, whenever carry isnot generated, an gives Combinational Logie Greuits 247 Teele i rity oil vtec aaa pith amemnae oI o,f Fi at oon | xample 4.7 (8) Draw the Joie diagram to find the 1s complement of & » Draw and explain the logic diagram to find the 1's complement ‘-bitnumber. ©) at Pit number, whenever the contol input M = 0, otherwise the output same as the input Solution “ay The 1's complement of a binary number is obtained, when each bit is subtracted from I or each bit is complemented. For example, the 1’s complement of 1011 is 0100, The logic diagram to find the I's complement of a4-bit binary number is shown in Fig. 4.26 a), Fig. 4.26(a) 1's complement of 4-it binary number (©) When one inpat of Ex-OR gate is logic 1, then the output of Ex-OR gate is the complement of anther input; otherwise the output of Ex-OR gates same asthe inputs. ‘The logic diagram to ind the ’scomplement of a4-bitbinary number when ‘M=0, otherwise same as inputs, is shown in Fig. 4:26 (b). isthe 1’s complement of B, when M=0 Cissame as B, when M=1 cs{Bit Binary Adder E B eteieds ee cco cn 4.266) 1's complement of 4-bit binary number, Example 48 Draw and explain the logic diagram to find the 2s ofa bit binary number when M = 0, otherwise the output is sameseu athe ing Solution Fig, 4.26 b). To add | to the 1’s complement, a 4-bit binary adders way nl Cy Case : Fig. 4.27 Logi z Ed 4-bit binary inputs ogic diagram of 2's complement of 4-bit binary i sant Cisthe 2's when M = 2'scomplement of input B, when M: 'Ssame as input B, when M = 1 “— ombinational Log Gests 48) iri combine st, hick poms talon he BCD ae pode theumia BCD Frm BCD aden can peroed sing ina? ald it can be converted into a valid BCD by adding 0110 othe shee dor the following example resol eee () 744-11 @ No 110 #BCD for 6 0111 #BCD for? 40011 #BCD for3 +0100 #BCD for 1 TOT elmvati¢ BCD ___110 saad QOOTOOOT +BCDfor11 FT ¢ BCD for 9 (valid) Algorithm for BCD addition "Add two BCD numbers using ordinary binary adition 5 Check whether the results vid or invalid BCD. 1 hihe result is valid (.¢. result $9), no correction is needed. 1 ifthe esult is invalid, then add “6” to get the valid result. ‘when the result is invalid, Y= 1 otherwise ¥=0. See Table 4 Table 47 Carry (Cou) Sh ° ° ° ° ° 0 ° o ° ° o ° ° ° ° ° ° 1 ° 1 ° i ° 1 1 1 An invalid BCD can be converted to valid BCD by adding 6, i.e. ad8 6 tothe result whenever Y= 1,220 Digital Electronics seadig From the above map, Y= Cou + SiS3+ S35, ‘Trelope diagram ofa BCD adder wing 04-bit binary adie Fig, 4.28. rar ean nat 4 4 Se i ip ieee Bate ‘Binary Ade Cou fonts (ae dit Losico Tens “ones Fig. 4.28 Logic diagram of BCD adder using 4-it binary adder ‘The 4-bit binary adder, add the BCD numbers A and B with carry = 0.Tke ‘combinational logic circuits designed such that Y= 1, whenever the resultof ise) adder, i invalid. When Y= 1, the 4-bit binary adder, adds 6, otherwise tad) and provides the valid BCD result. 4.6 BCD SUBTRACTOR In most of the digital systems, the process of subtraction is performed by usin ha state ‘The subtraction of BCD B from BCD A is equivalent ne addition of complement of B to A. In ion, 9° 10s ‘complement method is used, Eee tome ample. th Fore complement of ___ Combinations agi ceuts i je sts complement te pmplement of any digitcan be obtained by subretng the digi fom, compe 9's complement of 4=9-4=5 -3=6 se 48 sos the decimal digits and thet 9s complement, able 48 Table 4.8 TE 9-029 ‘omplement can also be obtained by adding (10)ioin binary tothe 1's st number. For example, (b) 1001 4 9inbinary 0110 #1'scomplementof9 ‘These complement of thi (0100 ¢ 4inbinary @ 1011 ¢ 1'scomplement of 4 41010 # Add (J0)oin binary + 1010 # Add (10),pinbinary “roror u (0101 is Sin binary and itis the 9's 0000s in binary and itis the 9's complement of 4, complement of 9. ‘Te logic diagram of 9's complement of BCD is shown in Fig. 4.29. Dy Px |Dy Pa Logic| ee sia ~ Ay By By B By 4-Bit Binary Adder 9°s Complement Output Fig. 4.29 Logic diagram of 9's complement of BCDarowsedtofindthe 'scomplement ory er ‘and the 1's complement of pe BCD, pr ORE fo der ads (1010 Boy Toi 2 lene! BCD MMPSF the ag, afmowe ay subtraction Recs Bich Ais oval M2 A +9's complement of “Ait tS Lt TicaTy BARONS cay Si rcaroat a ot edo the smaller number, theres Mh en ede the following examplon 7 (b) 3-9=-6 Acie Am le yas 0011 ¢BeD ST ancbfir9 SCD fora 1100 +B fem} +0000 $95 ropa TT eat BCD DOLE + Cinyngt saiio eaass il cldigt complet wort Lot + Addthe cary Result TTI0 + BCD fs cass Algorithm of 9's complements BCD subtraction 1. Find the 9's complement of subtrahend. 12, Addthe two numbers using BCD addition. 4. Check becary.Ifcarry is generated, the answer is positive and theconet ‘results obtained by adding the cary to the intermediate result. Otherwi the answer is negative and the correct result is obtained by taking thes ‘complement of the intermediate result. ae the 9's complement BCD subtraction. Four Ex-OR gaits ag are wed to finds complement of subtrahend. Adder 2, adder3,0R Me ee as discussed in Section4S and Ex-OR gates are used to find the 9s complement of the eth a lafterthe BCD addition; otherwise it adds the ca)” ‘onbinatonal Logie Circus f eaiAder — |S Rep Input ‘ona Cea ES Sa BCD Adler, Lose sl wreany 0 Binds eon atresut | |S DRAGr sign 0—> Positive Sea. {= Negative SS sia Sy [BCD Output Fig. 4.30 9's complement BCD subtractionppaoecrn_— . gh cota decimal digit is obtained by adding (10) pe vcomemetl a endationot 109'Scompleme iy see of Eider the following exampley, "Xdagp® ihe 'scome o's comple a ete 15 ant () 1001 + 9inbinay fo) 0100.04 miementof4 9110 6 1's com, sot) +18 . +1010 + Ada cig, To 14 (10a bay 110) gin 1010 ¢ Ai 116 Cary ng, Lente £0000 6 Di scar he cay SCAR the phon aad tint +0001 ¢ Add tinge smo ots 000 ¢ Bim "complemen AE orscomplement of + 10'scomplemeny spe loge diagram of 10's complement ‘of BCD is shown in Fig. 43), | fein 4s my CLL) nay Ader i a J ea TW Compleat Op Fie 431 Lose diaga of 10' complement of BCD ‘TheEX-OR gates wed to find the 1's complement ofthe 4-bit number The -bitbiar adder asthe I'scomplement and 1010 with the carry to getthe 10s complement ofthe orginal number. 4.64 10's Complement Subtraction Tessin five BCD dis fom, equivalent wo the ation oe sonnet fPandAie.A-B-=A+ 10's complement of B. isadedearecmetsabocton, when the 10'scomplement of asmaller numb rund cag ube aay generated, This cary is known asthe ene an scared get the comet positive result. Whe te ca Rumbet is added toa smaller number, ccarry is not Serie in 10's complement form, The comes! }sompleneothentermediat resol Conse ____Sembinational Loyic Cenits jag ipa @)3- ) 9-355 g BCD ford 0011 © BCD iors @ 7700! + Ey complementof3 +0001 #104 {Sorscomplementof3 +0001 6 10 scomplemento Ot a LL Cay, Uae ae 1 Spvalid BCD O10 ¢ Ca B [A=BlAcB ofofofojo | 1] o ofofolijo jo} i; a o}o{rfo}o | o }a 6.)0)) jae esp cot) on OL plo Not teal ae Outahees a |. 90) Sea alae Comparstor Salaalai a. |a. | opel Ce ae ee Pete a cca pe \6] otc lo) alle eae 1 |e WO: 1 ‘ Fig. 4.36 Block diagram of TO} 4) pak tea bene © mbit comparator TIE alaeO teed’, Cl sleet TY AC1O- |) Th, alti) oleae SoS |e. otts|: te ger i aU Sty |e 019 ale“fats te Aopead hh +4AoK, B= A,B AyB, + A AoB Bo + AvAoB Bo + As AgB,B, = A,B (Ay By + AaB) + ABy(AoBy + Ay By) HB (Ay © By) +AiBi(Ao © Ba) (8a © BAB + AB) (Ay © ByAs © Bi) AeB= AB, +H A By + ABB ‘The lope dgram of a2-bit comparator using gates is shown in Fig, 4.37, ee as Combinational Logie Cues pg 7485 —4-Bit Comparator A it compares the 4.4 Tn compare. 1 cmp the wo bay number, ha sa aie cascading inputs Le. A>B.A =B, sad AB. Te Neg Fe geo wnt oy eh Tine teas can bes 4.38. in Pie pa cs 2B, Bs By Bo As ha Ai My pelos iia a ADB A~B cB Fig. 4.38. The logic symbol of IC 7485, seth table of IC 7485 comparator is given in Table 4.13 Table 4.13. Truth table of IC 7485 comparator : ‘Cascading inpuis _Gompariog woats asm [a=m | Ace [asm eS is mo oe 1 ae] aoa aaa oc ok (fain | eee ia rey Bt sCia glee at col tone teen a eer Stones |e =p Tee ee “The functional diagram of IC 7485 is shown in Fig. 4,39 and the description of pins are given in Table 4.14 a 16) Ya. 4B 5] 45 ‘puis 4 4= 2 ia Aa A>sl 1 2 3 4 13] By A> BLS. 12) 4, 6 7 8 up 1 4=2! i) Asal 10] 4y onp| 9 | Bo Fig. 4.39 Functional diagram of IC 74854 <8 Cascade inpat A= B Coscade input | ‘ | A> B Cascade output J | a> soups re 7 | acdewt tes ae: Sait fap 411 Dosen a8 COMPUT UNE IO 7485 and Salaion [crsisa4itcompasr ths hee outputs and thre cascading 4>8,A=B, and p- i 443. Logicdagram of even panty generator 49.2. Odd arity Generator combinational lgie circuit that generate ‘Todd purty genertorsa combinational silo es ecg merc Te pary pete ae apa’ binary infomation and generates the paity bit O/ such ty a von of pry bite toa number of Is in the message becomes, ‘Tabled 6 shows the 4bitinformation with odd parity Table 4.16.4 information with odd parity -4-bic information Odd parity : ‘ 1 1 1 si i i oyt 1 . tl ii eas i alpha italia: vealed ‘4 Lake ite 14 ‘i Fig. 4.44 K-map for P with Seale |.<.2 inputs A, 8, C, and D “AB, Cand Dis shown in Fig. 4.44. AS be. pelosi Combinational 4ABCD+ ABCD + ABCD+ ABCD + ABCD + ancy paneer ABCD _AC(ED +BD)+ ACD +8D)+ACUD +BO)saccap + HD) _ATBOD)+ ACBOD) +ACBOD)+ACHO Dy = (AE +ACHB OD) +(AE+ATHB SD) F(A 0. OBO D)+AGOBOD) - (a808@D) +A @OKB®D) aeooeD) iagram of 044 parity generator is shown in Fig. 445, ones pb Fig. 4.45 Logic diagram of odd party generator 40 PARITY CHECKER “auhe receiving end, a combinational logical circuits used to check the paity of thereceived information, It determines whether the errors included the message trot The combinational logic circuit used at the receiver to check the parity of received information is known as the party checker. ‘There are two types of parity checkers: 1. Evenparity checker 2. Olid party checker 4.10.1 Even Parity Checker ‘Theevenparty checker isa combinational logical circuit. Ithas m-bitnputsmessage anda parity erroras the output. The circuit checks the parity of inputsand provides ‘the output 0/1, For an even parity checker, if the parity of input message is even, ‘then the output is 0, otherwise the outputis 1, When the outputs 1,itshows there 'serorin the message. The truth table ofa 5-bit even parity checkers given in Table 4.17. gay ens ae 5Table 4.17 Sbiteven party checker _——Fai neat ___tonbinationa tase Cieuts 957 pe = AED (COP)+ KBDCOP)+ TBD COM + ABDC ®P)+ABD (COP) +ABDICOP) +ABD (C®P)+ABD(CO P) DiC oP) + CHP) + AADCOP)+ XC @ Py ‘+ABD(C@P) + D(C®P) +ARD(CS P) + XCHP)) = (AB +ABYD(COP)|+ AC + P)+ (AB + ABD CoP) + DICBP)I(A® BXD © (CHP) +(A@ BXDO CHP) = (A © \DSCOP)] + (ASBYDS COP), =A@BECODOP re oie diagram of an even parity checker is shown in Fig 447, 147 Logic diagram of even parity checker 4.10.2 Odd Parity Checker oddparty checkeris combinational logical circuit thas m-bitinputs message a icraias liga Tpeesrat Seu tame eee een {fe ouput O/1. For an odd parity checker, ifthe parity of input message is odd, then the output is 0 otherwise itis 1. When the output is 1, t shows there is error nthe message. The truth table of Sit odd parity checker is given in Table 4.18, PE = ABD (CO P)+ABDICOP)+ ABD(COP) + ABD(C@P)+ A BD(C® P)+ABD (COP) +ABD (C® P)+ABIXC ® P) B[D(C © P) + D(C @ P)| + ABID(C@ P) + DIC @ Py +AB[D(C® P) + D(C @ P)] +ABID(C © P) + D(C+ PI} ABD (C®P)+ D(C ®P)} + ABLD(C®P)+D(CSP)) +AB(D (C®P)+D(CHP)}+AB[D (CBP) +D COP), (AB + AB\ D(COP) + D(C @ PY) +((AB + ABYXD(C®P)+ D(C SPY) =[(AB+ AB)D(C@P)+DC@P) (A © BYD OCP) +(AOB\DOCSP PE =(A®B)\DOCOP)|+(A@B)@(DOCOP) =(A®B)O(D@C@P) momConibinational Logic Greats ate a.ne_ sito pry checker me 230, ee arity checker is shown in Fig 4.49, times [Par fig. 449. The losicdagram of odd pay checker 11 PARITY, GENERATORICHECKER (1C74180) 4 eine sity generates canbe edt apy gener cise ase sty pts 1 and wa cueing 1 aes Even en 08 Tne mbek T7000 iornin Fig. 4.50- ern gf 7410 gv Table 419. able 4.19. Truth table of 74180 Cascading | Outputs Parity Boda Tae 1 1 0 | Cascating Tops ° 1__| Fig.50 Logical symbol of C 74180 From the truth table of IC 74180, itis observed that Parity inputs + Cascading input = Output Even + Even = Even Odd + Odd ‘Even Odd + Even, = Odd Even + Odd = Odd i SES eaen ‘When he cascading inputs ae Topic 1 then the outputs are loge NS 0 both cascading inputs are logic 0, then the outputs are logic! SOLS] al Kemap for PE with inputs A, B, C, D, PPei cae fig Ast_Logiediagam of it even party checker ample 140 Design 29 od party generator using IC 7419p, (hyDexgna 10-bit od parity generator using 1C 7415, ‘Solution setae party generator. has eight parity inputs, WO cascading iggy we amoes geertespaty bitaccordingto the 8 input Messages, Tela gon fait pry generator is shown in Fig 4.52 (a. i 2D | o-bit even parity ‘information ~4 A Combinational Logie ci a 2 | Soe ta 2 | oir py ee a al i po) | EBven | —2 | zou! |—oJ tors select one input at atime and send itt he ouput ine, Foran oe giplxer m elect inputs ae ese ir = 27. The block diagram ofan minput wirgplexers shown in Fig, 453 ie #53, Lisactivelow enable input. When hs input is 1%, the chip is enabled. sare rplexeris also known as a data selector. pepening upon the digital code applied atthe 1p ae ortines, one ofthe data inputsis selected and qased toa output channel. Tet us consider a 4-input multiplexer as an example. For a 4-input multiplexer, the number Sei S28 So ce inests two C2 = 4). The th table of a FB 4.53 Block dlaram of “4:1 multiplexer is given in Table 4.20. rminput multiplexer Multiplexer Table 4.20. Truth table of 4:1 multiplexer The expression for output ¥ ean be writen s Y=5,Splo+ Soh + 51S9l2 + SiSolsig 484 toricdasram 04 multiplexer using gates, ‘4.12.1 Multiplexer Tree pi st keer aval Form OTC yg ia Tet Te d2 aie at, ules 1Cs gma Cet st cae eae La mst ete tapes tag mas putt MEduee 102 palal a | sia 1 apices aa ms i tion ip Br te ie “Telus availble ICs of multiplexers are 16:1. Therefore, to implements rnp wth more than 16 inputs, there should be provision for expansive “Thema hasan enable strobe input, which helps i its expansion. ‘Letusconsiderthe example of an 8:1 multiplexer using two- 4:1 multiplexersas: area 55. The expansion of a multiplexer is referred to.as multiplexer Foran 1 mliplxer, the number of select inputs should be 3. The $1 wb) iS theenable inputof 4:1 multiples mit tr select input, Whenever Sis logic 0, the TCM, will pe enable i ra antes wpon binary input ‘and So, and one sea ouput, Whenever Sis logic 1,Myis enabled and: eee ees, and), and one of the nes able of 1 muiplexer using ewor4:1 muliplen®> _____ Combinational Logic cneuits gag ig. 455. 8° multiplexer using two 4:1 multiplexers one 4.21 Tra table of 1 multiples using wo 4 mules Sect ines Fnabied | Disabled ss r eens ™ ™ io slate |e m me h Aa aria Fac m me is a alae m mm i, aie es m m ie 1 0 1 mm m Is i asGlied mm mm . 1 1 1 ms m b Trisasopossbletoimplementan 8: multplexerusing 4:1 and2:1 motiplexers asshown in Fig. 4.56. Fig. 4.56. 8:1 multiplexer using 4:1 and 2:1 multiplexersns RE : table 4.22 Ponte gt Applications ‘many into one. Tt 4.12.2 Multiplexer is. device that allows plac ing diy ma soma single output line 28 er the seat iy ‘ombinatonal logic circuit can be implemented by yg intluplexers re widely sed and hey oat Mulplexer means information from 5 say application of nulilesers and ese following advanast 1. simpliation of loge express 2 teminimizes the IC count, and 3. Logie designs simplified ‘Te sgn pred of combinational logic circuit using muliplesrisg follows: 1 Meni th dina nmbercoespondingioeach minterm intheexpresion 2 Theint ines comesponding to these numbers are tobe conneetedtolo eve andal other input ins are connected to logic 0. 2 Theo these inputs are toe applied tothe select lines ion isnot required, Example 4.15 Implement the following expressions using @ multiplexe {@) TA,B,O.=3n(, 1,2, 6.7) (b) 14,8, 0)=11M0, 14,5) Solution (3) Ginen Boolean furctionis MA, B,C)=Em(0, 1,2, 6,7) le Boolean function, therefore a multiplexer with hse required to implement the given Boolean functi implementation using an 8:1 multiplexer wit! ofthe multiplexer corresponding to the £1 ________ Combinational Loge crests pag sare connected 10 Voc and other inputs nes recon are connected to proun me Mut E isconnected 1 ground (enable the chip. The inputs ‘Tweet Eas the chip. The inputs eee comecte the seeing ines of he mes ae Multiplexer Op WA,8.0) te af aks ABC ig. 4574) Implementation of WA, B,C) ~ EO, 1,2, 6,7) yen Boolean fretion i ¥(A, B,C) =T1MO, 1,4.) ibis athree-vriable Boolean function in ferms of manterms, It canbe aqessedin interms as YA, B.O)= E02, 3,6,7) itis tvee-variable Boolean function, therefore a multiplexer with weiget Hines is required to implement the given Boolean function Fgured$7(b)shows th implementation wsing a8: mupleserwithtree select inputs Gi Kec 8:1 Output Multiplexer | 744, B, ©) 2 ptes ABC Fig. 4.57(b) Implementation of Y1A, B, ©) = FIMO, 1, 4, 5) Y ‘The inputs of the multiplexer corresponding to the given maxterms are ipo rogecihe th peaee e is connected to ground to enable the chip. ‘The inputs A. B, and € are ‘connected othe select ines ofthe multiplexer. 2 sanje eto ample 416 sonnei Henle ePESIONS ig i. ao +a Ming, Ye zac +aBCD+ ABD + ACP Pe pride eee ake solati na venom exeresions qpC +ABCD+ ABD+ ACD natal Boinerecsn simul DCOnee i vim of products fo ia 1. Zatip + D)sABCD+ABDC+C)+AcoH4 5 ) =apCD+ABCD+A Amcb+ABCD p +ABCD+ ABCD+ABCD BCD+ABCD+ABCD = ApCD+ AB + ascD+ Al BC+ ABCD+ABCD+ K = ApCD+ ABCD +A OL=7 ABCD=0101 an expression can be writen as ‘Theabove Boole Y(A,B, C,D)= 2m, 3.4,5. 7,9) Vee lf || ia 3 ; i : aos 5 watt FBG) i iB B a 8 E S555 Fig 458) Stag Implementation of = ABC + ABCD + ABD + ACD Combinational Lage Gteuits sable Boolean expression, therefore a multp lexer with four jew four-vat ura quired to implenient the given Boolean fu he maliplese orexponding othe ier nasi and other inputs are connected og ‘interms are uts of Manected 10 VX reonnest ected 10 iscte treet ins of the mullet Gen Boncan expressions peas BCA +8404 B) sjetee-varable Boolean expresion in terms of product fs i ould be converted nto the standard for, ee yaa 4B+ CT) (A +B+O~UA+ B+ CC) © TiAaBt CntAtB+ OA 4B+ 0-40.44 B+ 0) AxB+C =00=0 A¥B+T =00 F4B+C =100=4 ASB+C =01 A+B+e =011=3 qe above Boolean expression can be written as YA, B, C)= TMQ, 1, 2,3, 4) rtisathree-variable Boolean expression therefore armultplexer with hr cexstng ih equied to implement the given Boolean funtion. Fi ‘ses the implementation using an 8:1 multiplexer. tion. Figure 4.58(b) Fee Q i 3 oa 3 é 4 Multiplexer | 1(4,28, ©) ¥ B e He tite seats ABC 5818) Implementation of Y= (A + 6)-(A +B + O+(A +B) Tae Be ‘corresponding to the given maxterms are coms : ground and other inputs are connected to Vcc. Theenableinput E is connected to ‘to enable the chip. The i Connected tothe sees ines ofthe muller RE248 os rt the following combinationay seca open toi mtn gg Be naar = 8 stat se sonata oes i yrs conbitotl CHC au “Tae up : Te la pea anc uP Th hing TREE sunt enn Tbe 4230) by radii Table 4.23(a) Truth table of hal-adder ne gts dfrence and boro, are Fanctons ong Aan a ato pesoscane rien ® ‘The 0 A % ae a tA, B= Em(l, 2) ! 1 ~ CiA, By = Smt) i ‘ es Fig. 4.59(b)- Anaifensdy he ie Yee - opus, sumand car. aethe functions of inputs, ang Teoma hs 5" ea ee ‘Sum (A, B) = Em (1,2) Carry (A, B) = Em (3) ‘These can be implemented using two 4:1 multiplexers as shoyn jg Fig. 459) fey ++Combinational Logi Gres 251 —_ —————— pe expression of outpot Ycan be writen as [y+ 5 Soh + SiSola + SiSals Solo 5 Sah + S150 ls + Sal Fulo- Soh Sole SSA wt 5 Silo, F4=3Soh Yo in obama 8 er A F = GB Sule SaSiSohr) -S251S12) « Sr5;S01) (S35, 551) SB Sole) SS Sy) (SSSI) etyeKe Ys where Yo= 53 S:S0lo Yi=S25iSvh Ya= S2SiSoh2 ¥y= 55,50 ¥42525,Sole Ys “Taking complement ofboth sides, F RVI NNN y= WaPo ‘The logic diagram of 8:1 multiplexer using NAND gates only is shown in Fig. 4.60(b). i Sols and = v=1hE ‘Thelogidiagramo4:1 muitiplexerusing NAND gatesisshowninkig 444 5,8 Fig, 4.60(a) 4:1 multiplexer using NAND gates (b) Foran 8:1 multiplexer, n = 8 and m=3. Let us assume Jp, I), 125 Fs Jay 15. eand fy are the inputs of the: and Sp, S; and Sj are the select inputs. The truth table of 8:1 mult given in Table 4.24 (b). ‘The expression of output Y can be written as. 2555 Solo + F550 + 5815p + SSS + S38 Slt > 5 ole+ $2 ia f+ BSS(252 Digital ectronics Example 4.19 Implement the following expre multiplexer 18 EXPFESSION Using > YA, B, C.D) = Bm(0, 2, 3.6.8, 9, 12, 14) Solution ‘Given Boolean expressionis YA, By C.D) = Em(0, 2, 3, 6,8, 9, 12, 14) ta ose onl Hla en toe EU efeion ogee la above expression sing an 8 I multiplexer. The aboweexpee tole Table 4.25(a)_ Truth table of ¥ =Em(0, 2,3, 6, 8,9, 1 2, 3, 6, 8, 9, 12,14) [wien [pie 4 2 @ mi : o T hm 0 1 0 1 “The relationship of input D and output ¥ for each group of two rows gives the last column of Table 4.25(a). Its found thatthe truth table can be wate terms of three variables as shown in Table 4.25 (b). Table 4.25(b) Truth table of Y using three variables a 2 é. val 0 0 0 D 0 0 1 1 0 1 0 Ht 0 1 1 D 1 ° 0 1 i 0 1 iD a 1 0 1 1 1 D Combinational Lagi iets B55 si] M.a.GD) Mux) ra usr pletion of Y= EM, 2,36 8 9, 12, 14) using 8:1 srultiplexe beeen mewent following expression using a single 4:1 plese ath B. C= DO, 1-4, 6,7) sola given Boolean expression is YA, B, C)= DMO. 1.4.6.7) iste variable Boolean xpresionnterms of interns An: mules scared to implement this expression. Butts also posite wo ‘implement the item ein sing a1 muliplexer. Te above expression canbe wren im ‘fetonm of truth able as shown in Table 42648). table 4.26(a) Truth table of WA, B, C) = Em(0, 1,4, 6, 7) i 1 5 =) Fig, 4.62. Implementation of YA, B, ©) = E00, 1, 4,67) ‘Therelationship of input C and output ¥ foreach group of two ‘he lst column of Table 4.26(a). It is found that the truth tabl ___lemsoftwo variables as shown in Table 4.26(b). The shown in Fi284 _Diotalslectrones ae ia : - - 0 i He epee 1 ‘i a the Teese % Example 4.21 Implement a full-addce using wo 4 mat Solution i) {A full-adder has provision to add the previous cary. It has and C1) and two outputs (S,, C,). The truth table or ee i Table 4.27(a) Truth table of full adder ee Combinational oie Ccuts gg implement a full-subtrctor using (wo 4:1 multiplexers, 421 has thre inputs (Ay By and C)aMt¥O outputs (Dy. C,) where 180" Sei sit and Cis he borrow ier ulster tenn Table 428 in Table 4.284) Truth able of subractor Tapas —i An By Cut S, at 0 0 0 o 1 1 ye 0 7 0 7 o 1 1 ° mt H ° 0 T 1 0 1 ° The relatonshipof input. and outputs D, and G, foreach group of worows 7 7 ° 0 jsgten in Table 428(). 1s found thatthe tuth table can be writen in terms of | Cut ables asshownin Table 4.28(b), Figure 4.64 shows ementationof : : : + al-subractor using two 4:1 multiplexers, i ‘The relationship of input C,_, and outputs S, and C, for each group of om is given in the last column of Table 4.27(a). Ibis found that the truth table can be written in terms of two variables as shown in Table4.27(). The implementation of the given expression using two 4 multiplexers is shown in Fig. 4.63. Table 4.27(b) Truth table of fulladder using two variables VocCombinational Logi hts 257 Bee Distal tectonics _ Example 4.23 Design a 16:1 multiplexer us (a) 8:1 multiplexer and OR gate (b) 4:1 multiplexer Souton (o ewe 465 shows the 16: mui inca Of gi. Fee fl pecs venconioecia of multiplexer is used asthe select input. 1 mon ties, Teng Fig. 4.65(a)_16:1 multiplexer using 8:1 multiplexer and OR gate When A =0, Mux-I is enabled and Mux-2 is disabled. The outpaa gate is one of the inputs of Mux-I according tothe code atthe slat B, Cand D. When A = 1, Mux-1 is disabled ¢gate is one of the inputs of Mux-2 B,C,and D. ‘and Mux-2 is enabled. The ou according to the code atthe select (b) Figure 4.65(b) shows the 16:1 multiplexerusing twod:t mitt” four 4:1 multiplexers are connected in series. The ena multiplexers are connected to ground. The output of Connected to 4:1 multiplexer; the select inputs ofthis 1B.igi letronies etatonl Se pote g Table 4.30 Demultiplexers me passion | TOT belies ota Sees | Sake ae oe Bunt 6 __| Sane ap : i] Gora 18 dentine sing two 1 demuiplexes as shownin ay exact niles, the number f select inputs should be 3. The ate ‘ rr jet inputs and hence the enable input is used as we Sit a ogo y acted abd abe an ei ctectnP eat San So the input it given wo one ofthe outputs, sett Pon SFG jsenabled and n sable: nd depending uponthe ever Si is given to one of the outputs as given in Table 4:31, Fig. 4.66 Block diagram of n-output demultip multiplexer Table 19 _Truth table of 1:4 demuiplexer [Seer inputs] re in fee - ae Ste neste arate 0 0 1 0 m o 1 5 ice 1 o 0 wey 1 1 4 ede ‘The expression for the output can be written as 55 Mi =5% Ya=85 ¥5=5,5) ‘The logic diagram of 1:4 demultiplexer using gates is shown in Fig, 467, Select Inputs St pS Fig. 4.67 Logic diagram of 4.13.1 Demultiplexer Tree “The 14 1:8, and 1:16 demultiplexers are available in the form 0 Table 4.30. - largest available ICs of demultiplexers are 1:16. tiplexer with more than 16 outputs, there should be provsi er has an enable (strobe) input which helps in its200 ( Srp] Bae | ie | [s. [ Ss [| : i %e Pog aap asneceey etal el fifofe| re fafa ic, fafa efi fo [oli Example 4.24 De (a) 1:8 de (b) 1:4 demutiplexer 1:16 demultiplexer using iplexer Solution (a) The 1:8 demultiplexer is also known as a 3-10-8-line decoder, j select inputs and cight outputs. To design a 1:16 demultiplexer, 1:8 demultiplexer are required. The logic diagram of 1:16 dem shown in Fig. 4.69 (a), The bubbleon the output lines are active low Iss the mo peng indicates thatthe ong Fig, 4.69(@) Logic diagram of 1:16 demultiplexer using 1:8 demultiplexer (b) The 4-t0-I6-line decoder can be designed using 2to-4-line decodersas hom in Fig, 4.69(b). Combinational Losi Creat eonllotietieits aa tesa 6d pee 5, Dealer 2P-—26 % sh—e7 fi 468) Loic dlagam of 1:16 demultiplexer sing ot demultiplexer 1425 Implement the following functions using 31o-8-line decoder re Zim(0, 1, 2,4) ¥yA,B, C= Dnt, 3, 5,7) ¥,, B, C= Em, 5, 6.7) Solution (Given Boolean functions are m(0, 1, Y(A, B, C)=Em(1, 3, 5,7) YMA, B, C)=Bm(4, 5, 6,7) ‘Tis moli-output combinational circuit can be implemented using 3-10-8-line ‘oder. The expressions of Yo, Yj, and Yq are inthe form of minterms. The OR {atesare used atthe outputs to OR the defined mintermsas shown in Fig. 4-70(@), The above circuit diagram is correct under the condition that the outputs ofthe ‘decoder are active high. But usually, decoder outputs ‘are active low, therefore the uputsar inverted and givento the OR gate. We have seen that inverted input OR fates are replaced by NAND gates. Figure 4.70(b) shows the logic diagram 10 ‘implement the funetions defined by the previous expression with NAND gates:Combinational Logie Cucuits ggg’ fig. 4700) implementation of furcion using 170 code and OR sate ig 471 Fuller ving decoder aa alt % J esign a2-it comparator sing suitable decoder > sample 42 48 K i comps ony an eons Te ahaet Bo— 5 Devote 4 ma iinet’ given in Table 4.33 coh 3 L compara 2 able 4.33 Truth ble of 2it comparator S754 Inputs: Outputs: a | ae | Ase ase | ieee 70(6)_ Implementation of functions using 0 Fig. a 3:to-B-line decoder and NAND gate 1 ° Example 4.26 Design a fllaer using 3-0-Sline decoder 7 Solution © ream adder has three inputs and two outpts. The truth table of full, 5 ‘in in Tabled 32, Whonthe inputs are 001,010, 100, 111, then y= and when . JpeinputsareO11, 101, 110,and 111,then C,= 1. Therefore the expressions fas, i and C,, can be written as * e Sly Byy Cot) = Bl, 24,7) 1 Ci Be Cut) = E35, 6,7) s rles2 Tt blo alr : Inputs Outputs ° ibaa Bese hss Sai |G L ope 9 0 0 ‘The expression for output can be written as 1 0 A 1 0 A> Blo, Ao, Bi, Ba) = (4, 8,9, 12, 13, 14) Bislets |} Ones ‘A= BUA, Ap, Bys Bo) = Em(0, 5,10, 15) ey 1 0 1 AS BUA, Ap, By, Bo) = Zan(, 2, 3, 6,7, 10) 1 1 0 0 1 t 1 1204. reimplementon of 2-itcompartor singa4 16 decoderigsy perish "in | | | era 44 —— 52 res Sls sh— a 5 8 ~——|% | 10 | " 4:16 Decoder i Fig. 4.72 2-bit comparator using 4:16 decoder 4.14 CODE CONVERTERS 4.14 CODE CON ae Code is the symbolic representation of information in a particular format, The information may include numbers, alphabets, and symbols, which men and maine ccan recognize. The basic property of machine code is its binary nature. The bitay representations of hexadecimal, octal, decimal are known as hexadecimal ce, ‘octal code, and decimal code, respectively. The codes are used to store and tans the dataefficiently, There isa wide variety of binary codes used in digital systems, Examples of binary codes are: 1, Binary Coded Decimal (BCD) 2, Excess-3 code 3. Gray code In most ofthe applications, it is necessary to convert the code from one foi a another. This section explains the various code converters and their design 4.14.1 Binary-to-BCD Converter BCDisa4-bit binary representation of decimal number. The 4-bit binary cos converted into 5-bit BCD. The truth table of binary-to-BCD converters gi! Table 4.34, JCD Ba, Bs Bo B Kap for By By and Bp with inputs A, B, C, D are: Kemap for 8, ot B= AB+ AC. Kemap for Byiia let _ Combinational Kea for By a able of oN otto ee ‘Table 4.35 _Truth table of IC 74705 wo] 0 a zi \C 74185 binary-10-BCD converter is given in Table 4.3, The logic diagram of binary-to-BCD code converters sh own in Binary Inputs aa oat mo Geah | 4-15 isnt 9 20-2! n-3 ues 26-27 2-3 4-35 ° ° ° ° ° ° ° 1 i 1 i= wot |! S enact 3-9 | 0 L —* wn {1 Fig. 4.73 Losic diagram of binaryt0-BCD code converter sot 1 1 1 1 1 1 1 1 1 x 445 IC 74185 45-47 It is a 6-bit binary-to-BCD converter. The block diagram of binary-t0-BC) a converter is shown in Fig. 4.74. 50-51 2-3 54-55 By fa)0 fe] (3) fE]o I} es c) eels] | 2 G E D Cc B 4 | es IC 74185, ea 45 7 ' i % y 2-63 Treprvpupa wo ere Ge Fig. 4.74 Binary to BCD converter (IC 74185A)____ Combinational Logie tees gag Digital Bectronics _ 4.2 BCD-to-Binary Converter Keep for os fc y BCD na my ci and te 3b BeDeode Pesta) | ann pce BCD 0 Diy eet Table 4.36. 5-it BCD and its equivalent Binary mage [=e eae Fe Pa AT Se oe g AAO Or Ro i Jet ils bess lado clea Hat eps | saa i feo {eo ops ot haemo i fae dis (oe) 0 lenenogeam f [ deo) | pet 15 tm ola of: fofofsfo}rfojs ’ | 1 fo qo, {oo Pbaoe it Hy osama ae i foo ffo fou) as) oft | ome ie eoeale Gd 0 joor |e) aaa map forD i foo dia fot | eh oe la tena een ve 1 fio) a foo 4 Uo} bela ie ie tala " rfpod idee fer eor tiie i fede} 1410?) eo ionh ome o p feo fea fea a (ona -0 bbl coma mea rift frodeo | 0. | te} 0.) bs) alam tifa do} a] a ae Pe: eRe Sie ae D=B,B,* BB, “The K-map for binary A, B, C,D.and E with BCD inputs By Bs, Br By ay Kemap fo Be, ae pin Kemap ford nator M108 00 ined et mioliey a tek eal T 450001110 BS | wl ofofxfo 0 o a afofo|x|o on u iy c nfo] of x} x i wl of o[ «| x wf ol of xix] wo] o | of x| x 10 E-By A= BBB, + BBs270 Distal etronics The logic diagram of -bit BCD-10-binary conver ~ rte is shown nF BCD Inputs 4 ty hh hOB ° oo | | | i | +—+,| ¥ Ht i Fig. 4.75. S-bit BCD to 5+it binary convener 4.14.3. BCD to Excess-3 Converter Excess-3 code is a modified BCD code. Itis obtained by adding 3 to each Bop code, as explained in Chapter 2. For example, the BCD code of 4s 0100 ant reese. 3 code of 4is 0111. The truth able of 4-bit BCDs and their equivalent exes 3 codes are given in Table 4.37. Table 4.37 4bit BCD and its equivalent excess-3 codes 5 ‘BOD Code Excess} cole Decimal Digit |g, |B, | Bo | &s | & | 0 0 10) Ogee Ol ae 1 oto, |p |e ait) a 2 of o (oa | On Oe 3 Oxted! 1 Pelee t= |=iiiae 4 onic leo| ome.) Sasa 5 eee en col 1 17| 7d 6 aaa 1 0 1. to eae 4 eallea alae ue [eis] Sela an 8 Belg ff eal 0 /te| 2 8 Healey dco | 1) 1.2] oa eC vex-3 codes By, Ba, Fv and with BCD inputs paces ans IPOS B, Bas iagram of BCD to excess-3 code converters shown in Fig. 4.76, ‘Te logic ding [BCD Inputs BB By Be Fig. 4.76 4-bit BCD to excess-3 code converterita Eeeonies_—_ Combinational Logie Ckeuits 7g asa Excess to BOD Converter vccess-3 code and ts equivalent BCD - i _authtable of excess-3 £04! is given iy The a aaeags ced code andi quale gc Ls Bee ea “Bxcess-3 606 aes Decimal Dit RET ae ES “5 : | fa [eon | Pee 5 ied faal it Ee | easiest £ tee ie BA Pe a : a ia dee uals ig. 4.77 Fxcess3t0 BCD coe converter | ; : i 0 : si /-to-Gray Code Converter salt rfijfol? 4145 Binary Sa tt ese cer ban ces Se ee cgacnsm encom “The K-map for BCD codes Bs, Ba Band B with eXcess-3 inpus By and Ep are: Kemap for Bs io able 4.39 ‘bit Binary and its equivalent Gary code oy rape aa Fen Dea oneteonniaay Fe] 27 ocaile- lou ees sua ao aaiaa Oe giT\ ie cee \eonsale ca a wot tle soe etek eecrs i aae Rte fete ei} eat AM bate (emiec ere. | ef ele wt scale eae Hie ener erswen learn (ten ce eS ee SAE ae oe ae o 0 oO 1 + 0 mi Dota flak weary Lice eyelid te at 1 1 4 1 1 1 i! 1 ¥ 1 rag att Laat ae helo Hess Vatt leas 1 1 By=Fiey* Bly Tay By pasate eel ce ‘The logic diagram of excess-3 to BCD code converter Is shown in Fig. An. 1 1 1 A 7 im ‘Combinational Logie Cireuits 4 e Gray code and its equivalent binary code £5 pay codes Gy Gir GirADd Gy WithDinary pay» able 440 Se ‘The K-map fore ons oe ” ‘K-map for Go Kevap fr as P fora, @ ‘inary codes A,B, C,and D with gray code inputs Gs, Ga Gi, ‘code converter is shown in Fig. 4, = “The logic diagram of binary-to-gray code ig. 78, chee a +8,6,= 6,96, K-map for D_ ou Fig, 4.78. Binaryto-gray code converter 4.14.6 Gray-to-Binary Code Converter ‘The tra ble of gray code and its equivalent binary code converter is givei# ‘Table 4.40. bisfi 278 % 1GTGN+ BAG #QGG Bod 2G, AGGirGe he G+ GGG G0 + GsG2G,Gy GG OG)+T,GCs®C)+ CGI, 86) 46 pram 3 ate GG GGG + GiGo) + (GX GHG, Gy +6; bey = No.8 ENG, x69) +(G,X CNG) ®G) (6,86)(G 8G) +, G48 6:06) 6) G20 ‘The los diagram of gray-to-binary code converters shown in Fig. 4ny GG % ; ie rh | 1 te leas Outpt Es Fig. 4.79 Gray-to-binary code converter 4.14.7 BCD TO SEVEN-SEGMENT CODE CONVETER Inmostofthe applications, seven segments are used to display the result. Thingy code of adecimal digit eannot display directly over the seven segments. Terest need to convert the binary representation of decimal digit (BCD) into sevenseast code. The seven segment display includes the eight segments, which areefente se th 50% Son 3 ti fore pcan BeD Combinational Logic Gucuits 1 equivalent seven segment code for con its equivalents He for common anode am ~~ ne input is 1. BCD codes and their equivatent seven x! zrype is given in Table 4.4) -segment ‘Seven segment code | as a,b, c,d, , fg, and h, The segment will be ON or OFF according to the input data, The seven segments are of two types: (i) common anode and (i) comm» cathode. Common anode ieieaianiensalb)ye'scven sopment te aoe of light exiting Oo (segment) are connected together to Vee. The segment is ON when the ip sole Blais etre pe | Jofr|a) a | olonox napa rites oFEMDIY P54 fg By Bo, Bis ad Bo ec jediast “retotcn Fig 4.80 iss" of ah .fBCD to seven-segment code converter for cor ter forcommon anode fat AR aoe eh —— 5, fig.4.80 BCD10 seven-segment code converter for common anode pe Common cathode nacommon cathode type seven segment, the cathode of light emitting diodes {ceament are connected together to ground. The segment is ON when the input is Tanditis OFF when the inputs 0. BCD codes and their equivalent seven-segment code for common cathode type is given in Table 4.42 able 4.42 BCD and its equivalent seven-segment code for common cathode200, _ Distal Hectroies_ mt, Combinational Lage Cre ____tenbinatonal ie Groat _ amp Kap for ‘BCD code dst 7 | Bs | Be] Dee i Mu Lt LI, fe BB By BB, ~ BE BBPydpe o | | eras | spy Leer a 4 ig. 482 Logic diagram-common anode dsplay Fig. 4.83 Logic diagram—common cathode display { 414.10 ICs of Seven-Segment Driver/Decoder a ICTH6A,ICTA47A, and IC 74LS47 are the ICs of seven-segmentdriveridecoder, Fij.f1_ CD10 sevensegment code converter for common cathode ope np aa and prove open cil oupusto dive _ jividual segments directly, Each segment has 40 mA maximum sink curent 4.14.8 BCD to SevenrSegment Display Decoder ‘apc. These ICs are suitable to drive common anode seven-segment display. Seven-segmentdisplayis widely used in digital systems. For displaying dataustg Figute 4.84 shows the functional diagram of IC 746A, IC 74474, and IC this device, the datahaso be converted from BCD to seven-segment code, LST. InFig.4.84,4o10.Agae the BCD inputs and @ to are the ativelow oupats ofseven segments LT isthe active low lamp test input; its providedto test whether allegments are working or not. When LIT isheld ow with RBO open oratlogic tip he IC drives al the display terminals ON, When the BI/ RBO ispalledlow, 4.14.9 Basic connection For Driving Seven—Segment Displays Figues 482483 sow he basic connections for driving a common sn display. In these figures, the resistors are used 10 limit the current. are wsedtolimit the sink current, whereas in Fig. 4.83.08500_ ithe source current ofthe driver.igitat Beconics Ic TAA6 a! ea A Aten SL oe |e ee ee 14 Functional diagram of IC 7446A, IC 7447A, and ic 74) Say Figure 4.85 shows the circuit ford riving a single seven-segment di a oa ay 5x I ee ae c 4 76 at |BUREO ‘GND Fig. 4.85 7446 driving seven-segment display “Theresistor Risusedto limitthe current. The value of resistors canbe calculsteds Veoc— drop across LED ~1x R=0 “The drop aross the LED segment is approximately 1.5 V and the cute! within the ringe of Sto 30 mA. Let us assume current = 20 mA, $-15V-20x10°xR=0 apo Ale 20x i ‘ata time. But in most ofthe applications, thereis techniques are used to drive mult Idisplaysa single digit to display more than one digit. Different fig. 4.86 Cascaed non-multplesed displays aking in multidigi ‘displays sale encandapnymarbersrm 0006959. ehare ea etapa OATS. Bt sould appt 45, For he ts 1 ead not apps. Te one diagram'o dla fur swihthe resing OF planking is shown in Fig. 487.plese Eco requires power ni ‘Mattple even seqmentaytem equies POWET7 LIMES the poy, Amit. repay erent number of even sep ing ‘sigs ts rey 2 A and fr seven scene FB opicy eng teen tng he mA ange SE shots a four-digitmuliplener display gy i, tei: CLOCK Counter] ‘ ie 9) y [hresisor Bank = [reisorsnk] [Resor en] sel fester eee 1 ee name jae | If co aco pep Fig. 4.88 Four-digit multiplexer display system Here, only one display is enabled ata time. But because of high speed, the ds would appear to be continuous to the human eyes and overall, the curren, requirement is equal to that ofthe single seven-segment display (140 mA), 4.15 PIN DIAGRAMS OF ICs (1) 74182 (Look Ahead Carry Generators) (2) 74L8283 4-bit Adder Ke For Z e At] a z [2 13] ‘ ab fa) aa B OEY rasa fi s[6 i) ao Lio) 4 af fs)s shmetic Logic uni) a= m3 a> Bla] a>aCs] a=a(6] Terass | 704, oxn[] * (8) 7485 (428 compartn) a] ra 1 111 shoal or example, O00 . complet acd adder wsine 7483 IC “LU can be constructed from two 741g MEE Whig 1p. Desi 8 : wan 8-H ied ing fonction using 8:1 MUX: multiplexer: foes 3 tao nt ee TB I 0. esi the fllo fl ser ws 71. ele SiO, 1,255.7, 8.9.14, 13) 15, Design a fe on 2-bit magnitude comparator, 21 sm0 CD? i 16, Wee a sho Ey generator fora bit MESSABE Code ladder using to 4:1 muliplexes jgn an os pari aia pine gubtactor using two 4:1 multiplexers, har four inputs and ON OMIpOL The ou jement# is 23. meg. MUX usin () 8:1 and 2:1 MUX peta | diene ane ae je cau Desi, MUX and OR gate ta Aconti : ech 2 en a amber of inputs are equal 101 . y at ees ; (pe ollowng fonctions wing 3-o-tne deco ete En, 1.5.6) (0) (A,B, = E04, 5,7) ein ’ ind the simplified Out M4 ouiput funtion in sum of produets form, ‘ (A.B. jput function in product of sums form, Yate = Ent, 3.4.6) 9-3 code converter using truth table, K-maps, and logic @ Fi ow help agra for sm of Products equation in i tgemet olin fonction with an 8:1 MUX: noes’ reer 7) =2aO 1a 5.89, 18) cig ne folowing code converters (4B, = 202 4,5.7) 7. ies roe Gi Fi (@ Binary ane afi mine 220 {oir to Excess 3 (@) Excess-3 to binary J@ BOD to Excess-3 (®, Excess-3 to BCD (@ Binary 1 erey (h) Gray to binary Partll {Design a 2-it comparator using logic gates “tbit gray-to-binary converter using truth table, K-maps, and logic 1 beg combinational ogc cit wi four Input variables that wil pa ‘tut when the number of Os in input is even. ms pesien cri. Muitiple-Choice Questions loge 1 j.bign a combiational logic etcuit with three input variables that wi rade oi | ouput when mote than one input variables are ope | os 4, Define hal-er an fll-ader. Ina having to ip A and ands opus Sand Cah so 5 Desig ahal-adder using NAND gates onl. oe ‘its, respectively), the Boolean expression for S and C in terms Design afll-ader using NAND gates only eee “f ve E () 5=AB+AB,C=AB (0) S=AB+AB,C=A+B A+B (© S=A4+AB,C=A+B- (9 S=AB +AB, 2. Fora binary hal-subractor having two inputs A and B, the cores set of loge expressions for the outputs D(= A minus B) and X(= Borrow) af wm () D=AB+AB,X=AB (b) D=AB+AB,X=AB (©) D=AB+AB,X=4B (@) D=AB+AB,X=AB 3. The logical expression Y = A + AB is equivalent to .. 7. Define halfsubtractor and design it using NAND gates only. {Define fllsubtactor and design it using NAND gates only. 4 9 Draw and explain the block diagram of an n-bit parallel adder and explin is limitations. 10, Draw and explain the carry look-ahead adder. 11 Draw the logic diagram ofa 4-bt subtractor using 7483. 12, Daw the logic diagram of a 4-bit ALU. 13, Desin the 4-it BCD adder using 7433. 14, Design the 4-bit adder using 74181. Show the working for the following cases () Y=AB (b) Y= AB a) A=6, (b) 4=9,B=8 5 ; y , =9,B= (© Y=a+B @ Y=A+B ; 15, Desig 9b od parity checker using 74180 and suitable gates. 4,The minimum number of NAND gates required to implement A+ AB + ABC 4. oe iy abe wing 75180 ‘sequal to cae ee eso 4 10-bit even parity generator using 74180. @o (o) 1 O4 @7+ O=AB+ACis : (None of th J Boles therein °C AB + AC at BatO is frequently used for add f for addition, becay () is more aceura is faster @ (@), costs less ses fe a miemeated with bal-adders an __ atic tomponnet wi al er tnd OR au, nial cay Tequies adder without 29 ae i gas and OR as) Saran og Stan OR aes) Thales dg oR aie i soe in ICA te OUP depends on ration at that time the ‘and input combination gates 4 ‘raat ey Acoma (a) input comb he previous output vous input ad nat © err and the previous outPut ng circuits paalle-t0-erial converter? () decoder (@) multiplexer ot co tere (a) presen 9, which ofthe follow fo digits counter (© demltplexer sen lel ous he re 0 ABE OHA of hg combination at that time cacode is (@) cca code () excess-3 code (e aray code (@ BCD code decimal number 125 is written as (@) 000100100101 (@) none of these 11. 8421 BCD code the ( 11101 @D Wo oe Bolan vibes, how many Boolean expressions ctn be an be form @ 16 (© 256 “ (© 1004 @ 64K a L@ 20 3. @ 4@) 80 6) 72 @ 8 @) 20 10. @ IL @) 12.@ raptor SEQUENTIAL Locic_Circurts eee, Chapter Outline ‘ent memory ca 3s a yp of fHP-TOPS. oer giggering used In Hiplops op a at ret steno sa et spe ae revere uN sree arc never aaa! nd er «tot fe a128 ONE" 2D yeu ert 15 ara Mealy 6 si eke saver Ct ss eocked soquenia orc De ne agra and sate abo Teton ecigue and sat essgn 5.1 INTRODUCTION smite previous chapter, we have studied the basic concepts of combinational logic Gecitand its design. Let us now learn another important digital system known as tscuenfal circu Inasequental circuit dhe outptis dependentupon the present ingats swell a the past inputs and outputs. The sequential ciruits include the ‘memory elements, which store the past inputs and outputs. The flip-flop is a bit val tree Lope Co ee memory ised for further tion. This i pi ela Se ‘This chapter includes the study of 1. SR flip-flop, 2. IK flip-flop, 3, Master-SI I-K fli 3 Maser Slave 1K fip-flop flip-flop, and 5. Dilip-fop, ;sige seamaster a A Sen rp te a eisai aplication sya conse. in ‘ese gs well 8 m a the presen NPS ata. The ip OPS basic element of sequent ieee Sic Using ipo eal be s car) ton oui Sc, ay sey a Geol | crit can be designed. The pa jeer | tock diagram of sequenng se og revit is shown in Fig. 5.1 Theor Samat of memory een et ar A ‘may be given san input to conto esa eck row outatothe syn sy circuit ‘theapplications, the outputisaf a aco fe upterconbiaional presentandpstnpusoly ei mien spe ans Tests ies mea 4-pit MEMORY CELL, swostates,oneis logic state and ance spams nase inl cay es nas 0 Sig A ee aio The eo ing ‘suega be sed sa ipl. The 1bit memory cell can be obtained by using ‘tamsistors, NAND gates, or NOR al. cmmatsequental ic fig. 5.3. ‘bit memory cell with external contol input a. When inputs are = 1 and R'=O; then T; goes in saturation and T goesin Waste The output of Tis Vee su= 0.2 V, say logic O state and the outpt Sf Tois Veo-say logie 1 state, and the flip-flop is said 0 be set 4, When inputs are $= 0 and R= 1, then To goes in saturation and 7; goes in Tatoff The output of Tis Vce ax =0.2 V, say logic O state and the output ‘fT, is Veo. say logic 1 state, and the flip-flop is sad to be reset 4, Wheninputs are S= | and R= 1, then both the transistors try to goin saturation, which is not possible, ‘The truth table ofthe circuit is given in Table 5.1. sing Transistors 41 using transistors is shown in Fig. 52. ‘ON, due to small difference in he of (a othe transiosakes more cient and goes saration he tier goes inct off, Lets assume transistor T; goes in saturation and Ty inca ft the ouput of; Vora =0.2 V, say logic 0 state and the ‘output of Tis Voc SN clic |stats Both he stats are stable. This circuit doesnot awed conto inpat andthe oupatof ciruit cannot be changed. ‘hel -bitmemory cell withanexternal control input circuit Operation areS0andR=0, then heres nocharigein state. TCU the previous sate, 5.2.1 1-Bit Memory Cell Us “Theciruit diagram ofa I-bit memory ce ‘When he switch of power supply is Table 5.1. Truth table of circuit (Fig, 5.3) itis showninFig.53_——, gree — - agit? |AND Gates “ cell Using N bit Me Teor el sing NAND B83 showy, sec oneee ny TaleS inte aoa able 5.2. Truth table of fo Gig 54) BI diag reas 0snd R=0, en Doe cups of ge Ga Ga 1 eam | Daod R=, possible Ter isarace betwee he kp, ree penetra Ca . y is said to be reset the memary is said 1 5.2.3 bit Memory Cell Using NOR Gates fa L-bt memory cellusing NOR gates shown inFlg 55) “Te gic diagram sarin rh nieis given in Table 53. Table 5.3. Truth table of logic diagram a ie @ (Fig. 5.51) s|R Q a 0 | 0 | same as previous [Same as preview s. oft ° 1 Fig, 5.5(a) 1-bit memory cell 1/0 A, 0 using NOR gates rfa| Race Race Operation 1. When $=0 and R=0, then the output remains unchanged. 2, When $=Oand R: then the output of Gs 0(Q=0) and tat of G8 and the memory is reset. 3. When = Land: tenth output of Gis 1 (= 1 and tha of: andthe memory is cl. ian i esr aear R 53 = pap toni vo thenthe outputs ofa [-——} 08 =i erhichisnotpossble, |S 2 + eset, avecn the OUtpUts. i ser eninFig. ss@)isaiioknown ——[X__D}— je citer ol of a simple latch wit " sei Te Fy SO ih Fig. 5.50) Symbol of Te a ane is shown in Fi SR flipsop ot e ep SR FLIP-FLOP _ - .ock! ibe setor reset any time by changing the inputs Sand Hemand the memory cell set or reset in synchronous. sin thing but a train of pulses. The clocked S-R flip fications d ne clock is No Nes ack ot in Fis. 5-6 owe 13 ae aK % ro Fig. 5.6 Clocked SR flipflop Ore eek ent CLK =0) the cue ‘of both the gates Gy and Gare 1 cee change in te outputs of Gy and Ga When the clock is present sa pe ons of and Ci are the function of the inpasS and R. then the outputs of Gy and Gyare 1 (R’= 1 andS"=1), ‘and Gare unchanged. and R= 1, then the output of Gsis 1 and thatof Gyis0(R = Land Yep the output of Gis Oand that of Gots 1. The lip-lop is eset. 4, WhenS= and R=0, ten the outpotof Gsis Oa that of Gis 1(R’=Oand ¥ =the output of Gis and that of Gas 0. The flip-flop is set, 44, When = land R= 1, then the outputs of Gs and Gqare 0 (R’ =Oands’=0), and the outputs of Gy and Gp try to tecome 1, which is not possible. There Table 5.4 Truth table of SR isarace and the output is undefined and flip-flop itisknown as forbidden state. ‘The truth table of S-R flip-flop with clock isgivenin Table 5.4. This state is represented. a"? in Table 5.4, where S, and R,, are the Hest nputs,Q, is the present output, and ste capt the clock, The clocked lp-opis simply referred as S-R flip-flop.ip-Flop With Preset and Clear Input, oped ON. the output tate ofthe Mp Bl are a fooe elo the me ‘ie, ouput Qs eH be O or 1. There is Initial ogy. Cpe xed, ity Be a need to uae ten tn ton sv til oma Preset and clear are the adaiiet Mao nem cnn fei So fp WAP Alay : When the ip-fop 857 Preset, eee te Sere grrr =[apl—.2 ne Tee Fig. 5:7. SR flipslop with preset and clear inputs he stan eset npt are ange wn he lek ABD ANd when cei pate cone st et noi oT they nade ae stats Pf ep inp can change ot tbcckinpt snd ence thes inpus rekon yarns np chrono iP cer tnetbe ouput of G8 Landa of Gi anes independent of inputs Sand R, and the ip-flop is set - danny lar”, the output of C8 Which make be When oie O20, whieh s independent of puts Sand, ade Flip op ies aoe and clar=1 ten outputs of Gand Gp depend on tr saree Forma operation, reset and clr are connected tli 14, When preset = 0 and clear = 0, then outputs of Gand try to become | Here, the uncertain state occurs and hence, preset = Oand clear =Oisnot used, ‘The symbol of $-Rflp-lop with preset and clear inputs is shown in Fig. 58 and the truth table is given in Table 5.5. Table 5.5 Truth table of SR flipslop with preset and clear inputs hee Input Ouipat s SR a fe exee xe 5 ; alee if rg af ofo fi of} 4 Ba 1 ae wv Fig. 5.8 Symbol of $-R flipsloP ijt 2 with preset and clear inPus ‘Sequential Logic Cncuits 2 eset and x fulp-fLOP eee ae scrip ops overcome in -K Tp-fop. The lgiediagram of nin Fig. 5.9. ‘Preset, el Clear Fig. 5.9 Logic diagram of K flipslop spe outputs ofthe ip-lop are connected to the inphts. operation ‘iene clock sabsent (CLIC ), the outputs of Gs and Gare | and there is no nats of and G, When bectockispresen(CLK-= 1) the outs song Gua te function of inputs J and K- Phen J=0 and K=0, then the outputs of Gand Guar 1, independent of Mraraputs ic. R’= lands’ 1,andthe outpus of Gand Gareunchange 2, WhenJ-=Dand K= ,thenthe output of Gis andthat of Gxis0,. iy = 0,and the output Q=0andQ = I,andtheflip lopissaidtobereset 4, When J= 1 and K'= 0, then the output of Gs i O and that of Gals Lhe, FcOand §’= 1, and the output Q= 1 and @ =0, and the flip-flop is said tobe set. 4, When J= Land K= 1, then the outputs of G3 and Gare the funetions of caer inputs. (i) When Q=Oand @ =1,then the output of and that of Gy=1ie. R’=0 ands’ = 1, and the output Q=1 and Q =0. Gi) When Q=1 and @ ), then the output of G= 1 and thatof Ga=! "R= Lands’ =0. Hence the output Q=0and Q =1-isshown in Table 5.7 and pe ih bl of i 9P in Fig. 5:10 th able of CMPAOR a 1 rable 57 ‘Output 1S R flip-flop the J-K Hip To shronous inputs which Sets aly, as given in Table 58 Fig. 5.10 The symbol Similar tothe Servmnarieerteaitel preset and clear sy resets the flip-p init ables Preset nd Clear inputs stor reset he FUpslOp _ Outpt Fe co 2 F 1 Not used 3 1 set 4 0 Reset \ 1 Normal operation 5.4.1 Race-around Condition ‘The tuth able of IK flip-flop shows that when J, ‘Thats forJ,= land K, = 1, the J-K flip-flop acts as a input Jj,= land K,= and output Q=0; after the propag: (itistwiethe delay of NAND gate), the output will change .aJ-K flip-flop, utpatis connected to inputs, this output acts ‘asinput,andafterthe ‘next delay, the output will change from 1 10.0. This process ‘continued anda lied clock pulse, the output is uncertain. ‘This situation is know? asshownin Fig. 5.11 ‘where isthe duration of PAs = Land K, = 1, then Ore toggle switch. Considerthe ation delay Ar of flip-0p from Oto 1. Sinceit ‘i ono ie fli ine sper me sip! ite “Theoutput of tagh AND gate. Sq =Jq Qy and Ry fi SR flip-flop after the NOT is applied to the second $-R flip-flop. When ‘CLK=1, the first flip-flop is enabled and the ‘ouput of first flip-flop changes as per the truth table of S-R flip-flop. | 5.11 Race-around condition ofthe feedback, the input changes during the clock pls : ea ge ee ee sity oF a err -flop (0 Me ye ips fot hn. nein ie bee cee adie rene be er oop oom tn pate ae See aia a Teta ohege greeter pa plied ck panosecond slave |-K Flip-Flop flop using S-R flip-flop is shown in Fig. 5.12. fig 5A? MasterSlave J Mlipslop using S fipslop second $-R flip-flop is given tothe input of the fist S-R flip-flop = Ky The clock i directly appliedto the ‘second flip-flop is disabled. Thenear ae ip-flop is the input for 1 ip-flop and qn he input as given in T OP HOP and the ga nthe problem able 5.10 Operation of second flipflop gaa tp Top cae hah gg a tent tone oo eg je, Hence, the first flip-flop is known as Magen? 3 Hold ie eam cockrequene) Fo) s.a Propagation DeleY scp ange when the lock i 3 int Hence, he organ 4 sa hemo eee the state after the clock niet ojo = ji a er SEE” 5.8.2 Set-up Time Jnimum amount of time for which the input Ta pnd ataconint value before te clock edge arives, as showaig Fig 5.26 Thetypia valu of set-up time is from Sto AO as. I the set-up time of th signa se than the desired set-up ime, then the response of Hip-epis me reliable “The set-up time is defined as the mi Fig. 5.26 Setup time 5.8.3 Hold-up Time i “ woh gr pps, ut changes wih te rising edge of ot mean that after the rising edge of clock, the ‘inpat ity. The input signal shouldbe held atleast ‘Sequential Logie Circuits ead uae gn ste minimum amount of ie fo which heipa acon pong the inputs the switching time of teal zs i fold-up time is from 0 to 10 ns i; Baten. THES rye ypieal Hole WPS from 0 to 10 Cee 0 ras ro me cuk- fig. 5.27 Holdup Time sqm Clock Fremmency go ni ey wane opin an ig pen requency tat can Be plied asa CLK input for proper and eg i Tip flop is eiven a8 So 4, ~setup time of ip oP ste, = propagation eley tae of flip-flop 14, =propagation of next see decoder 4g5 Asynchronous ‘Active Pulse Width estan clara ative OW asynchronous inputs, These inputs are set0 the Pesca of ipflop by applying negative pulse to one of the inputs. ep wii em duran TRS ETD ido et te inital conditions of flip-flop. 586 Clock High Pulse Time and Low Pulse Time ‘Thee high puletimeis the minimum time for which the lok mostresinn) thse. Similarly the clock low pulse time {is the minimum time for which the cickmast remain in low state. 59 FLIP-FLOP CONVERSIONS: sats igsible to convert one flip-flop {nto another with some additional circuit, Theflip flop conversion includes the following steps: Sep I: Write the excitation table. ‘ep 2; Simplify the excitation table using K-map. ‘Sep3: Draw the desired logic diagram.acre rretronics_ Jop to T Flip-Flop for S-R flip-flop to T flip-flop «, 1 $-R Flip-F 5a ection abe p> 1 sip ye 5.14 i "tiv Meese cin ter SEINPHOP DT Heng — F Flip, [input | Presi lip-Slop inpurg sep 2: The excitation table is simplified using K-map. K-map for R Oral ok of x [0 ipo | & flop using S-R flip-flop is shown inFig.528 Kemap for S 3-10, ‘Siep3:- Theloieiagram of Ti Tlipflop using S-R flip-flop a Sequential Logic circait 309 Zeit D Flip-Flop table for $-R flip-flop to D flip-op conver oe ot ip 5 Excitation is table for SR flip-flop to D flipsop convers able Fig. 5.29. D flip-flop using SR flip lopae 6 Vv ‘Sequential Logic Circa ‘ pe = i a ™ got op to D Flip-Flop et fo plop LD ip-sop conversion wo gag saint Fs Flip Hoe | 93 SH eee RDO Topcon ct see rule 516 ee ama * so able 5 1+ exctation le FT Hipp 16D pop conver sation table for SR Mlipslop to HK vases excmon nol ft RAPA OH Cpt —T present | Newt a state inputs toot | Trt py, Tieeseiaion table is simplified using K-map. Mh ‘K-map for T table i simplified using K-map. Sep 2¢ The excitation Kemap for mane Xoo 1 oko ou ao |e ‘o] | x [oo veto] ob] ilo 5 5-10, Step 3+ The logic diagram of J-K flip-flop using S-R flip-flop is ee is ip-flop using S-R flip-flop is shown in p58 Dfinsp ig T Bion 595 D Flip-Flop to T Flip-Flop /T flip-flop conversion is given in Sep: The excitation table for D flip-flop to, Table 5.18. Table 5.18 Excitation table for D flipslop to T fliplop conversion Ge ¢ ite using S-R flip-flop——_—_—SS— eS sg1z_DiatalBestones table is simplified using Kes Sequential Logics ag, a Sep 2: The exci Keay forD r oat D=TQ,+79, : = +72, ‘oo | crest B 1 ‘vep 3: The logic diagram of TMip-flop using D fip-lop is shown iy py mesa, Fig. 5.32 T lipflop using D flip-flop 5.9.6 J-K Flip-Flop to T! Step I: Tre excitation able for fp-floptoTNip-fop conversions ivnig Table 5.19. Table 5.19 Excitation table for }K flip-flop to T flip lop conversioniat eto sntable is simplified using K-map, 2, Theexcit ow ied Fr xD eto digramof fin -opsins}-K M0-DO sshoyn np "8.534 Fig. 5.34 D flipflop using | flipflop xample 5.1 Draw the output waveform of JK flip-lop fr the inpu sy in Fig. 5.35 vn i) ifthe flip-flop is positive edge-triggered i) ifthe flip-flop is negative edge-triggered fr Leos ogl Sa yee Fig. 5.35 Waveform Sol ‘The truth table of J-K flip-flop is given in Table 5.21. Table 5.21. Truth table of flip-flop Description Same as previous input. Flip-flop is reset. Flip-flop is set. Output is complement of previous output. | jp waveform Fig. 5.36 1-K flip-flop Solution fur, G, and Gyare the NOR gates. These gates are connected such thatthe logic rvitetsas a NOR latch, Assume that the output of Gis R and the output of Gy iss ‘From the given circuit, we can write the Boolean equations, R=K,Q, and S=/,0, Qusi=R+Q, = K+ On Qun=S+0, = 5°0, et Quist ouput of the cit befor the sock and Qs He ours aN he_— ines — wy, and Ke NOR atch es when inp z R 0S Foran S Hence, Ore! 0. + wen ins y= 1 ad y= Osten = =0. Foran -RNOR atch segue bes we 0 1 Hence, Orsi = ! ifinputsJ,= Land K, = 1, then: ‘ Toran -RNOR ath [s20,| =O. an L 0 1 0 TD 1 Hence, Qui = Q, ‘The truth able forthe given logic circuit is given in Table 5.22, Table 5.22. Truth table for given logic circuit Input Output 2 K Qnst S 0 rm 2 1 0 ‘ 0 1 __Seqentia Logie Creits gy Fig. 5.37 Logic circuit [NAND gates. These gates are connected such thatthe logic Hat pare the! 20a Or atc, Assune the ouput of Gis Rand Ga act 23 equatons from the given circuits ee hoe and S=h+ On aneho 2, When inputs f;=Oand [p= 1, then S=1+Q, and R= Qy Hence, Qpat = 1 3. When inputs /, = 1 and Ip=0, then $= Q, and R= 1+ Qn ForaNAND latch,fig. 5.38 SR flipslop using D flipflop the logic circuit of S-R flip-flop using T flip-flop, raw uote 5% ty excitation table to convert the T flip-flop 0 $-R flip-flops given in he logic circuit of S-R flip-flop using D flips iP-flop, Example 54 Draw t Solution aan pecscition btn convert he ip 0S Fip-op ivy ‘Table $.24 : 4524. Excitation table to convert D lip flop to SR flipsop Table 5.24 Excitation table 1 « i Present State | Next level state | Flip-lopinpay s R a Qnot D fey 0 0 ° ile 1 1 1 oft o 0 o nec 1 o 0 1 aloe 0 1 1 1] 0 1 1 I inal ° x x ae 1 * x K-map foe 7 ‘Step 2: ‘The excitation table is simplified using K-map. Kemp forDSequential Logic Cirey nial Logie Cirewits gay able is simplified using K-map. Ker fork $5 eames S-R Mipfop. eH jeceuitot SR fip-op sing slop istowin ig 549 ars : oe Fae SR Alp fop wing THipop eam 54 eo ea IE MPEP OS phy satation nian ne 1 saver the 4 slop Sen Henin Tb 826 710 SR Bl- raties26.Excaion table 10 co7NeR HK POD 10 SR pgp can ae Tt [Pate [Pleo ira ig. 5.40 SR flips using }K fipfop Sra ies aga Je7 Draw the logic circuit of JK fipop using T Mip-op eet aa Toa sat r es sted lazer lope ea oe Peconic et the J-K flip-flop tT Aip-lopis given in |. ; o [o ofo valceat Saag ee oe | eee eae hee 1 aie lot 0 E eae ree el eras a ie o | o 1 az ).0| 1 1 xo : ae, — oe: x x x real: afig 51. FX flitlop using Tfiptlop gic circuit of J-K flip-flop using 8. Draw the logic Example 5: Solution D Mlip-iop, aon ale convert theDMp-op04-K Hip-Nop igi Sen: Thea val va s20 exciton wl coer SA 10H pp Prasent Sate | Nevt level ate | Fip-ap ap 7 Q Dae D af ee # 8 ° o | ° 1 q 1 0 1 o ® o 0 1 1 0 0 1 0 0 1 i 1 0 1 1 1 ual ° 1 1 dae sypp2:, The excitation table is simplified using K-map. K-map for D Fig. 542. 1X fliptlop using Dflipslop appLicATIONS OF FLIP-FLOPS 0 ie = pete one Fp can be used in i) Bounce elimination swite, (i) Registers, scarry woe 401 Bounce Elimination Switch 5 electors, the iputsare given asTogic Or logic 1. Theseinputscanbe ye oscillator orby themechanical witch, Switch ouneing isonet the important problems when mechanical ‘switches are interfaced to the microprocessor ‘system. That is, when the switch is thrown from. k Sy a a Ween #8 fig,543. Switching circuit indict cone position to another, itbounces several times, and the system gets incorrect data. ‘Consider Fig. 5.43, When the switch is pressed, the data given tothe system iseither 0 orl ‘When the pressure is released by the user, because of spring effect of switch, the input ‘changes between 0 and 1, and atTast becomes 1 as showninFig. 5.44. This problemisimpossible toavoid ina mechanical switch. The fip-flopis used to avoid the bouncing problem, Thebounce elimination switch using a simple S-R latch is shown in Fig. 5.45.fig, 845 Bounce elimination witch Using simple Say analy the switch sat position A, the input Ris Oana Sis 1, he con and ois When he switch thrown fom Position A to positon esto and goss 00: Q=Oand Q = 1. Because of sping actin yo oe fora anal ration both the inputs Sand R become | ng A is unchanged, as shown in Fig. 5.46. the og ie Dol c Fig.5.46 output of simple SR latch LLetus considera time f, the switch is thrown to position A. S goes to | and 205100. Qs land @ is 0. Because of spring effect, the switch may be open Bale the inputs and become | forasmall duration and the output remains unctange 5.10.2 Registers ‘The flip-flop isa I-bt memory cll, which stores the data in logic 1 or) form. The W-bitfp-flop can store N bits of data, On the other hand, rests _sfre more than -bit dat. tis composed ofa group of Mip-flops. A “biti flip-flop is shown in Fig. 5.47. fig 547 4bit hit ester using Dfipflop ter inpat connect to ground to clearthe Mip-slop an then, n timputsare connected to Vec. The datato be storedis given tesa awl stored with negtive edge of theclock, which can counters «ga sequential circuit, which counts electric pulses Itisused to emia The transuer converts the evens int let ples, which ready the digital counter. He somposed of ip-lops. Te logic diagram of a3-bitdigital counter 5.48. cout He ‘ante cou “recount ‘sshown in Fi: Fig. 5.48. 3bit digital counter ‘nacounter circuit, the flip-flops work as toggle switches, The outputs of flip- tap change with each clock, and the output ofa previous flip-flop becomes the tdoskforthe nex flip-flop. The n-bit counter can count" clock pulses.For example, ‘4bt counter counts 2* = 16 pulses from 0 to 15. The design of counters will be «discussed in Section 5.18. a ee e and preset inputs are connected to Vec. The outputs 030, 0oaf the counter will change with the clock, as shown in Fig, 549. Wiha——, ss 212 ¢ 29 Outputs ¢ Tass wes f 3 atl counter ‘seca withthe negative edge ofthe input clock. i Te output Qo changes with the negative REE ince Oya Rat tte oti arte dn pve ce of tha of ie lane 0 negative edge of Or 5.10.4 Random ‘Access Memory enya db development of cesicoadee a flops. The size of memory defines the number of registers and the size of word se eager. ach rege cae baa defines the numberof flip-flops svign adres Te memory isalways defined bythe equation Mx where Mis the aumber of registers (oration) and Nis the size of word. ‘The digital data is stored into ‘and retrieved from the memory. These writeand ‘read operations are done ina random. fashion and hence, the memory is said tobe random access memory “The memory has Mx.V basic memory elements known basic memory cell is shown in Fig. 5.50. ‘The decoder decodes the address and selects one of the locations. For write ‘operation, the data to be stored is given to the input D,. R/W control signal g0°s Tow. The output of gate G, changes from Oo 1, since the flip-flop is positive ed triggered: andthe input data is stored. ascells(fip-flop). The ss the RIF signal geshigh. Theoupatothip-sopis availabe arom alr 1 REGISTERS. AND SHIFT REGISTERS ae nat a lipflop i T-bt memory cel, which stores io gta syewve seen ha Hops stores more than I-bitof digital data eo i tal ata N pfs can gal dat. Ana of ip-lopiskoown a regi, which ine set ana variety of digital Stems sagt pe entered and retrieved in serial or parallel form the serial form ai (one bit at time) and parallel fom means al the is are sam i eteved-On te bis ofthe way the ata sented (wie) and sane theese ae clasiied as, T ser In Serial Out (SISO) + srl n Parallel Out (SIPO) 5 parle In Serial Out (PISO) 4 Parl In Parallel Out (PIPO) tester in which he dats entered andlor etrevedin serial formare refered swash register. 5114 SISO Shift Register ‘naSISO shift register, data is entered and retrieved in serial fashion with clock. ae of a.4-bit SISO shift register using J-K flip-flop is shown in infig. 551, X,is input and Y, is output of the shift register. The process of ‘lng digital data starts with the least significant bits, The datainputisentered ‘ahi alling edge ofthe clock pulse. The numberof clock pulses required to sequal to the length of digital data or the sizeof shit register. The ‘aiseadbit-by-bit atthe output Y, with clock pulse. letusconsidr the data 0111 is applied tothe input. Table 5.30 demonstra is entered into the shit register. The waveforms of shiftregstr for shown in Fig. 5.52.fig 5.52, Weveonms of shift register fr serial input Operation ‘The inputs of flip-flops D, CB, and A are X On. Oc, and Ons respectively. All Fists operate as D ip-lop andthe input applied is oul. Initially, the shift register is cleared. Qn0cOx0x=0000 and input X= 1 1 eee pe otefitcock pulse input daaisentereim0Ns flip-flop and atthe end of first clock pulse, QrQcOs04=1000 and input X= 1 “ofthe second clock pulse, theimputs ar entered entered and at teeta clock Pa 2A eo 0 1100 and input X= | HDI ce tlc bs et we ne __ ADE ne look Pe ak eget tne oO" gene fotos inp a eran 4, aume ee th clock Pulse He i oe J Tepiser,m clock pulbes are roquired 0 msiso sult re quired to enter the data and sont requeg tore eda explained in Section 5.11.3 aa tae aquired to enter the n-bit pont uc repens men at sree To gr vquied 0 oad tem al pn it will be lost 2 ne ye datas reads 3, one iz siroshift Register posites data isentered int theregistrin sera fashion, asinSISO aS read rom te shift renee ‘parallel fashion, In a serial output sit elock pulses are ‘eaquired to read the data and once the datas read it “aie rost bat Srparllel out shift TERS, ‘clock pulse(s) is not required to read Ye asnand te dat va etained after the read operation. The logic diagram: ofad- tei it eile sin D flip-flop is shown in Fig. 5.53. Cr % % Fig. 5.53. 4it SIPO shift register using D flip-flop Inthe figure, Xis the serial ipput and Op, Oc. Qp,and Q,are the parallel outpots ofthe sift register. 5.11.3 PISO Shift Register us tei ct seaeiinpenel SS andistead in serial fashion. -are two types of parallel loading: 1. Asynchronous loading, and 2. Synchronous loading3% vigil qos ing POPS register with async Herpes ti sos rons ena Initially. are giventot Togic 1, the output of fo flip-flopis set for Jon flip-flp st registers without the clock pulse, Such typeof pr ‘Theinputsare write “abit PISO shift re toa known 809 it-by-bit by applying bit-by-bitby apy athe data stored ina shift registers 1101 anditwite Forexample, le read fromthe outptt shift register. The waveforms ax 2 1 sesetinputsareusedt01004 the dita sm sy, ho, x with asynchronous loading, someting te lar inatt round leat De MD- Ds hig 7 i ine parallel inpots (Xn eli gt scomplementof input the Preset inputs acing Ko X-and.X,4)and the presetis.co resets connectedig Ya changed for |. The datais writen nto theregiy Toading. The data is tead from output ins y mnchronous ise. Once the data is read, it will be lost the clock pul ay able 5.31 demonstrates how the datas read frome rt hiftregister for serial outputareshown nig. 555 aoe __ Sequential Logic tines wots gay) 2 @ | O | | ¥ — J) ApoE | 7 hes 6B, and Aare X; Op. Qe, and Op, respectively. AIL ep ipflop and he input Xi Tosi 0 pf reser sores 110! 21101 A edge ofthe frst cloek pulse, “0110 and output Yo=0 edge ofthe second clock pulse, go11 and output Yo=t 4 ate eave ceo te third clock pulse, Qn Qc2a2n= 0001 and output Yo=1 14, ate negative ede of the fourth clock pulse, pQc»0a=0000 and owtputYo=O ocanit PISO shift registers” clock pulses are required to read the data and coc the datas toad, itis lost synchronous | loading Jngynchronous loading, the input datais entered in parallel form with clock pulse ‘Thelogi diagram of a4-bit PISO shift register in synchronous mode is shown in. 556. ‘a control signal is used to control the operation ofthe shift register, ‘when Sif Load is atlopic 1, the datais read from Y, bit-by-bit with the clock rake, When Shift Load is at logic 0, the data inputs Xi, Xx Xs and Xi load ‘simultaneously with the clock pulse. Such type ‘of loading is referred to as synchronous loading. Consider the data input is 0101. itn skfv Load signals 0, the outputs of gates Gy, Gy, sand Grate 0 and ‘heoutputs of gates G2, Ga, Ggand Gare same asthe inputs 0101 The outputs of Oise, ad hese are the inp oD ips is ae ino Ne ‘egser with the falling edge of the clock pulse. pons. ‘and ourput Yo= 1 ae (0900c090s= aSof apse ByRChonous nen Snitv Cond is 1 the ouput of tes Ga, Cre Osy ed Gy are, outputs of gates Gy, Gx Gs, nd G, are X;, Qs, Q2,and Q, The outputs of Ona uo ts ose ego Hp ope oe sr orth ine fling edgetbe ofthe ek Pale Itshows that the datas tty in the register and we get the outptt : ified 5.11.4 PIPO. Shift Register ve dataisemered as wel asreadinparalle fashion, There eno et of pul ee eetones Ini PO show g. Te loi aes ling PPO sown in ig 558 InaPIPO register, Sequential Logic Chcuits ggg Tolima a Wishes Up,Proit res er hex | ised sa i jrectional Shift Register reper the otaishiedinste Geions org sn Eye online hebben it ie jg spown i? Fig. 5-59- eA sina bh tees yO Gs,and Gy arcenabled, The wet ioe the input for Mip-flop B, the output of flip-flop Bis the ee upto Tp fn Cie np T-opD, and Xp ati? pa, Data i shifted ight withthe clock pe, UT, eotrol signals ow the gates Ga, Gu Go and Gyare enabled. The Eco tne inp of fp-op C the ont of Hipp Cis the ono of pop se ‘of flip-flop A, and Xi. is he Rp. Data shifted eft wit the clock pulse, Fig, 557. 4>it asynchronous loading PIPO a. Fig, 5.59. 4-bit bidirectional shift register ‘Application of Bidirectional Shift Register 4p Debi tei eu " n Tis not shifted out of register. For multiplying a number PY 7»—_—_——S"S—<“ | ; ooo soe es #001 Oshited fy 1bitwith Xe =0 sae cp 1 OO shied itby 2b with Xy = 9 sata proven hms significant iss Fordividing a number by 2% the datas shifted right bythe ap winaia 0. Fovexample, consider the number Toaded in the shifty and we have to divide the mumber By 2° 1000 1000/2 0100 shifted right by 1 bit with Xip=0 (001 Oshifted right by 2 bits with Xi. si 10002 In this process, the least significant bits lost 5.11.6 Universal Register “The universal shiftregister operatesinall possible four modes (SISO, ipo, Fiscal also as bidirectional shit registers. The logic diagram of a4. register i shown in Fig 560. Its operated in all the modes, but nota bid shit and shift register. Xs ronan E I xe—{0,?"0y cox a o CLK Yeo Fig, 5.60 Universal register In Fig, 5.60, X;is serial input of shift register, Xia Xp, Xn» Xe are four parallel inputs of shift register, Y, i serial outpot of shift register, and Yon Yon Yous Yoo are four parallel outputs of shift register. |CATIONS OF SHIFT REGISTER _ Sequential Logie Greuit pions ci iter titel lo costes converter alo ceial converter eae" 2. PE counter 5 eon 5 sams erator and detector + Fee om 5 Fy tne Erez Paraliel Converter 4 Ser one secsver ie esves the dati by Nt and then 1 se om, TIPO shitter isued cone dain Hea NS ert siz ofthe words hits. TheBLSTPO siege rm. CMS it with lock pulse. A he end of Sth elock pls, the erst a ye over the eight output lines ofthe shift egiter tt sai 2 parallel-to-Serial Converter 5 jeation, the transmitter circuit gets the snunication, the gets the eightbits of data, and then se ie “The PISO shift register is used to convert parallel data in er sei fO™- 5.123 Ring Counter ‘sot showsthe logic diagram of a4-bitring counter The SISO shitregister Fat ng conte. he ctpt Oconee ote sepa Ky ax Theoutputof previous flip-flop isthe input for the next flip-flop and suai pt on poy ctl le iniltregisteris 1000, How the data is shifted inthe shift register with clock pulse isgienin Table 5.32 and the waveforms are shown in Fig, 5.62. econ) Gt inl ona cre on Fare oie Wick ile Ties is known as aring counter. The outputis: at Qs, Qa Sale gaat of w docsrnig Gackt aetna Bae Ete33 Digtal ectronics Table 5.22 Data shifted in ring counter ~ igi iaiy saceansale Ghee rscmartcin neon oan ’ ee x [ate Teta) ° TanStigg lip rang 5.16.2 Excitation Table of J-K Flip-Flop “The truth abe of -K flip-flop is given in Table 5.48 and the excitation bei given in Table 5.49. Table 5.48 Truth table of K lipo Table 5.49 Excitation table of liplop ZF Ke] Qe [Present ouipul] Next ouput 0 0 Q. Qn Ques { Se [ie o 1 0 0 0 fo]x 0 1 |g ‘ z : 1 ares | 1 " a 1 1_Ixlo (0->0)transiion The presentstateofip-flopisO andthe nexstae of ip Ms vaio shows that ther is no change in output, J-K is (0, 0 "the mB 0, the inputof J Hip? {flip-flop isrese,J-Kis(0, 1). Thus for the transition 0 (0,0) or (0,1). Itcan be written as (0, X). gk ee 26 represent site fp ops and neat 4 fent output is the complemer el yt ee Plemenl of previous sen ste pp ws} KS(0) Thr hevenen Hetag De) New ion ‘Te pesntstateoTipsopisadthenextste oft. A qn pest tet the compen’ of evo capt an pon ee.) K's (0.1) Ths ford tenon {0 1 ee pop (1, 1.0, Kean be writen a, ae (Hos : oe cise yah 1 AA 10) Ts ores 11 einai wan ont tn 0 plop Kis tthe * ga eaitation Table of T Flip-Flop 168 fier Tip opisivnin Tae SSOamhecxcinon be gen mess! “ase regal Tl tele ot aa [Present ouipudl Next ouput] Tapa oF Qn Devt Ty, 0 or ° 0 ° fi a 0 1 1 1 o \ 1 \ ° p-ojrnstion The present steffi episO ante eso ep ge in ouput, is 0, Thus forthe transition i p00 Ttshow’ that there no chang food he inpat of T flip-flop is 0. (¢-stranstion The present state offlip-lopis Oand the nextstate of ipso PT eshows thatthe present output is the complement of previous oupu, 7 sph Thus for the transition 0 to 1, the input of T flip-flop is 1. (1 20jtransition Thepresent state of flip-lopis Land thenextsateofflip-lop is0-Itshows that the present output is the complement of previous output, T {s1Thus forthe transition 1 to 0, the input of T flip-flop is | (1 Dtransition ‘The presentstate of fip-flopis L andihenextstateoffip-lop isso L. I'shows that there is no change in output, 7 0, Thus fr the transition tothe input of Tfip-flop is 0. 5.164 Excitation Table of D Flip-Flop ‘Thetrath table of D flip-flop is; given in Table 5.52and the excitation ables given ln Table 5.53.a econ ssa fl Fable5.53 Excita wn The presentstateis Oand the next state isl put Dis 0. Thus for the te 552 Tash able of D (0 0transi ea clock, the ip-flop is ese Fut of Dflip-lop is 0 “Thepresent state of flip-flops O andthe next 1300.1 show, aston at = 1)transition or tate of) Pir er th clock he ip-0Pi83, D's Tha er ge Dio the input of Dip fop is | theta ftevo tamiton The present state ip-opi and bees, 1 eNartaer the clock theflip-Alop steset,Dis0. Ths tor ihe n> 1 tO the input of D flip-flop is 0. trans th otirasion The presentsiteffli-sopis and tenet ata 1 an gerne cock, he ipl set, Dis Ths forte yee? ten Po the input of D flip-flop is 1. 5.17 SYNCHRONOUS COUNTER DESIGN Inasynchronouseoune,theclock pls sven simultaneously oa hey andthe transit +e sthe otputisinsynchronisma with the clock inputs, Theda sone of synchronous counters as flows ein 1. Find the numberof flip-lops required. ForaModulis-M counter, the number of flip-flops required is, such a mst. 3 ‘ tis moted that an r-bit counter i also known as a modulo * counter ‘Wie the given sequence in the form of present state and next state ie-0 and Oy) ‘With he help of excitation table, find the inputs of flip-flop forthe gen teasiton 5, Prepare K-map foreach input of flip-flops in terms of output ofthe flops and simpli. 6, Connect theinputs tothe flip-flops as perthe simplified Boolean equations Example 5.14 Design a 3-bit synchronous counter using J-K flip-flops. a 3. 4. counter three flip-flops are required, n =3 is given in Table 5.54, ofpresent state andnext state with theenctatontle et — Neat wa Be Glo [elas ge eee Sie fe lala ls le etsy eke fat = eee Lee he late Heo: \ro:.|-x?) ae alral onan Be lioalte ttl kalo locales ee te lvoe fees ase tte Peal cst suas ae |e seal Saale eno se al Se tele Kemup B= 210 ‘The3-bit synchronous counter using J-K flip-flop is shown in Fig. 5.92. ee 477 Oy 1, P04) ck CLK Ki, 8 or ‘ i aeital ectronics —_ na Mod-S synchronous counter using Example 5.15. Desist ST Ning, Sequetia og bs, umber of flip-flops required in a umber of lip-lops required is re cnt be namber of ipo ree Anco ee me Rept S28 Se oe formot preset stale andnen sale wihthexiationtie cei formof preset sateand neXt With hg ce yen in Table 5.56 Fstop given in Table 55S. long sts otis aon? 10 pesent sate and nex tate wih ection table of Aipop les 55_ Pro sed nes Ste with aon be fg ile 58 Nextae ira Se TSR eee ee at yi rf OL Te DTD, Pree 3 = ee ee a [ote maples [or | oo | a eons | tale.) 2 aeaeeoss econ emule ct] es) yas Pie ct fe Pa aie nea lat Cabomlei\y oo |1 | ole | oka fy | o oe ale d ay Waele ot) vee ft belook a Ve eee lobe Ou Aly a ee | pit Vt \oo | oly file y mea etal 270, | by PRAY Gol \ oa sacle hy lt lies 6 Aaa) wii \o to | obo i\ios)a aol Soren ts) - % ° Paeou algo |. \-9. [a Lot feo ahaa 1 0 a 2 1 ees |e ho pro fb apt boda 1 hee Ber) o ae Pama toy. (a-th.o 13 lets | elle ba i hate aca WOVE joo jololols late fe lbitoel 5-6 en a t}o | 1o}o jo lo}olo lo lolo Ls toes der [0.0 lco-}0.}o Vio. \'0} 0 r}t}P lo jojo fojololo lola 24 i Wea. ooo] 9 fo Poll ao abo 0 Kemap fe Dy Kemap for, ifo 22, 10 3 aT TO 010, “a “The Mod synchronous counter using T flip-flop is shown in Fig. 593, 1 ot (2ey x igi ronous counter using D Mip-lop is shown jy rhe Moa 12 snc minis, Ss Fig. 5.94 Mod-12 synchronous counter using D flip-flop ce 4 oF decreasing ection as per designed to operate for mone hes rovidedto contro the operation rot inputs ao opeiton Let comnidr con which controls the ditetion of th noting Wcounee When ce Seg 89°07 ye ghrection of counterisin decreasing deton and he ir rm cuter Wien UP/DOWN apts hed tect gg reson hte cuter Seana comer Te it UP DO GIN synchronous countrispvenin Tale 55 “ot table of -it UP/DOWN synchronous counter 7 sate able 55 uriowN | a esontae of3-it UPDOWN coir for A ipsops is Genin ‘ble 5.58. ‘able 558 Exctaton table of it UPIDOWN counter or hyee, As sige tecrnie a8 10> + 0104 Kz- M010, + 0,0, sgram of a 3-bit UP/DOWN counter using J-K flip-flops is shows The logic in Fig. 595 5.18.1 Commonly used ICs for Synchronous Counter ‘The commonly used TTL ICs of synchronous counter are given below. On the basis oftheifeatures, ICs are classified into four groups: group A, group, eoup Cand group D. Group A: 74160. Decade UP counter 74161 4-bit binary UP counter 74162 Decade UP counter __ Sequential tose co fig 5.98. >it UPIDOWN courter using Hk fiplop Group B: 74168 Decade UP/DOWNeoumter 74169 4-bitbinary UPIDOWN counter Group C: 74190 Decade UP/DOWN counter 74191 _4-bitbinary UP/DOWN counter Group D: 74192 Decade UPIDOWK counter 74193 4-bit binary UP/DOWN counter 5.18.2. 1C 74191 ;cruigtisa4-bitbinary UP/DOWN synchronous counter. Ih anasynchronous ‘eet npat btn clear input. The Functional digram of IC 74191 shown in Fig 5.96. Op Qc Qn, Re MAXIMIN Pees feed 74191 Du Po Po Pp Py Load Fig. 5.96 Functional diagram of IC 74191 NAB: Itisan active low enable input signal. The chip gets enabled when his ie, ee eee. bea a setion contro! input signal Itdefines the diectign gg a 15-N) from 0000 Tpner and counts from 1111 0.0000. outer «diagram of divide-by-2 counter using 1074191 foc yp, DON ee aL > 74191 is a positive ede i! The ciesnown in Fig. 5.97, counting (exe iis cockpit. 1C 74091 8 apostveede-tggered 4 mode 8 Ce Onptschange whe te lckTs changed ong BONY Uy i ale hese are the 4-bit outputs loge ae oe 1 signal, Normally itis in logic 0 : ax pete Sota et SAIN sete Ny IO amg STN ten count eincoverow in UPcounting and underflow npg DIO Pp Po Pa Py = ‘ coun “+ It is the output signal. Normally it is in logic 1. It g0€8 to logic ‘e a = Be jx MAXIMIN pointandthe clock inptis iow. =? My ta ——! Toab-anaieow pase NID cede iq'597 Dvidey'2 counter sing IC 74191 for UP counting einer Tt shook be in loge during count ¢ Theseare the four asynchronous preset inpus. These design a divide-by-5 counter using IC 74191 for DOWN countin otetsonmer 43 messes | Ete ve oF singthe auton ae patona table of IC 74191 is given in Table 5.59, Fou = Fol ‘where (I << 15) for DOWN counting Table 5.59 Functional table of IC 74191 Fal5 = Fl =5(0101) Clock Enable Load | De Ee 2 1 ie x top oa ‘The circuit diagram of divide-by-5 counter using IC 74191 for DOWN x ° ° zm Preset counting mode is shown in Fig. 5.98. | 1 a a. # Up count t 0 L Lieve Lovs al : ie 2c Q, 2, Re Applications of IC 74191 ae ‘74191 MAXIMIN}—@ IC 74191 can be used as.a programmable frequency divider. In this application, the R-outpu is connected tothe load input and the required output waveforms bteined atthe MAX/MIN output. The frequency of the output signals funcia ofthe input connected tothe preset terminal. The relation between Fy, Fal Nis Fig. 5.98 Divideby-5 counter using IC 74191 for DOWN counting Erample 5.18 Consider the input frequency of the signal is 600 Hz. Design the circuit using 74191 to get the output frequency signal of frequency 60H @) in UP mode (0) inDOWN mode Solution @ Given Fox =60H2 and F,=600 Hz Fou = Fig/(15-N) where (0-< N $ 14) for UP counting 60 = 600/(15 —N) N=5 (0101) where (0<’< 14) for UP counting where (I< N’< 15) for DOWN counting, Example 5.17 Design the following frequency dividers using 1C 74191 (a) Divide-by-2 for UP counting ® ‘Todesign adivide-by-2 counter using IC 74191 for UP counting, In-KQu Ky=Voos and ¥=0,0yx ‘ See satstate, the nex state and the output ofthe sequential logic circuit for Present ate ae ate apa 8 a Ge [te [Reo [Re | OT ep eos ° neon | O! | T] Or torre Table 5.63, i Taeeeyet|-0°|°1..| 20% Man: z Next sate output 1 Meee | t | o.| 0 1 oF “Present i sabe at ie tos [pO Sf Gt [ta |e [Te Tee P| E Lu pm . “Te present lat, the next tate nd the output ofthe sequential ogc 0 gr te ag ATS See ae for X=1 is givenin Table 5.61 —< ty A, | Grileiig\BO°.) |: 0h teen a Table 5.61 1 De es ee ee aa RECS 1 fee Dae oelel als [ols \a the ala ea @ Gn |e lem] & [a | ‘he presenta, the next sae, andthe outpat ofthe sequential logiecicutfor ° fit iole|.] 1 | o | 2 terse 0 Reso 0 fast oo) coal ia 1 Medco joli| + Oe Table 5.64 1 fist Ois| Ube DSpood 100. o lo Ee ‘The state table for the given sequential circuit is given in Table 5.62, Kal Je [Ko | O | Q% | Y_ Table 5.62 vlo {4 ® i a Next sae 0 powell ahewienl eek ¥el ie0 bares Pha toes aah ate cs Bets | Grp Oe [ee oe Pola ee emer Peeecho | 1 0 | 0 Bie aio e}..0...| 0 Banal 0 ( Bee iiobe.| ! Onisah aah gil. 0 Bees 0 o 1ital Becton ven sequential circuit i given in : Table 565, er hem 11 ‘The state able for Table 5.65 Y=D,thenextstte [romtane’ [aa] jaye [o |o 14 i 5.20.2 State Diagram ‘The state diagram is «graphical way of representing the stae table, Thy, o fedoras aaron ae iva trace withthe sat indicated inside the circle pie a ee cncaee te te Deas Conon a ic eng numbers separated by the symbo) ()—C)—C)—@) itaieted tines, Tere thetpit andthe ita a indicates the output. Thestatedine nt” Ge) eMancomers tomar O—O—O ‘When prsentsse soa i001 andzoon Tse Fg5.308 Se dager 28H a une theme te capa state only. bitte ‘These dram fra plow is show in Fi. $109, Te cantatas anupcoune, 0, terse the cuit css adowns ‘When the present state 000, the next state is OO1 for X= 0 and itis 111 fora], Fig. 5.110 Sate diagram for 3-bit upldown counter pease of Moore cicuit the outpts nota funtion ofp, thereforethe dsted tes wih only one bnhy number, hich repose he ste he es put stat i indicated within the citele below the presen stat, as en 0 Fig. 5101 weate sate diagram. technique, reduce the numberof s min binary, assign Binary Values to ego cach able, da 3. ting he state rot + aripestmesare not ve eae wexplaind in Seton 522-5, mete th uber of tsps eared Implenen table ee mesons fr tn cen sperie ste ae ag fip-A109s ne >. Using Knap. 4 cuipat of Hip-0PS Draw te logic diagram 2, From thesta ein simplify and write the Boolean eq GUKIONS for the npg 8 5.214 State Diagram S21 ee poten a cst geet lope est i eto starements Te sate diagram orden Ca ‘informa ca state diag sa np utpt vate and low of transition a oy unberorvroblesnside be crcl represent the Sale The i cra engl or two binary numbers separated by a the tines are labeled wit ‘Whendirected lines rel valucthat causes the state! ane he valac bere te sybol ‘bt Inpat ale that ci oe ‘umn and he valve afer the symbol ‘/ isthe output val. ie 0,2,4.6, 1.3.5.7, when X=Oand P= 1 eres gonecnsa iste a 7,5,3,1,64,2,0, When: rag, Fignfs 112 shows tsa pai the desired clock sequential circuit. nomi and circuit Fig. 5.112. State diagram for clock sequential Sequential Lage cic cuts re state Table “ine output andthe next sat of sequen squential logic circuit foratt 521 57 ea ns oF present si Sf Naas pr ve), We ly Age coisa oa om hop lysing a clocked ei ection 5.201 ifevit-The paces Mpeked sequential circuit, Jocked sequential crcl, the state table is obtained fom c aga 00 a gate table forthe sate diagram of Fig, 5.112 aan 5.1 2isgivenin Table sob Table 5.66 State table for state diagram (Fig 5.112) ‘hes i) 00 4 Fig. 5.113 State diagrampig esronioe 7 é aa a je 68 Sable for ste dag i. 515) meer tae oe) Beene re ere er 2 SEA 5 Helene) ‘ ma cellule a eece heel a teal Me a\ aoe 7 £ Ae a fielder Reduction (338 |eaesh ieee dhdetermining the namber of Table 5.69 Moalified ste table acer wth determining De Mobe ofp. top ‘eden umn Using ate edocs y Cre Reon the numberof states. Thestale juction technique avoids the redundancy ‘Preset Sage acer tena ae vot sotes, we have 0 identify equivalent ymca 2 Eee rec the nub pee a z He th equvlent ats ar found, one oF hem maybe a enttea ete a aering the input and output relations, inte ae valeeaa ep i ie wate diagram of a clocked Sequential circuit, a, oy a ea ila Fig. 5.14 = “a Hoaipe nl elas intl, the tae dandfae equivalent ad enc, fisreplaedy dante emtgmove rom the table s shown in Table 3. Table 5,70 state able with replaced by d ext sate ut Present state | xa9 | xa | Xoo @ ea Nee. alls » Jo eticale Goal € aera | ee a « |o{i | o ‘ ot {| a lola 5.21.4 State Assignment ‘The clocked sequential circuit is defined in terms of present state, next state and ‘beoutput for different input conditions. The input for flip-flops are calculated to sgetthe desired next state for the present state and input(s), hence there is aneed to ‘specify the present state and next state in binary format. ‘Ifthe present state and next state are specified by alphabets, then binary values ‘reassigned for the alphabets. The number of bits used to assign binary values 0 ‘lphabets depends on the number of alphabets used. If the numberof alphabets is sthenn-bits are required to represent the alphabets in binary, such that2" > M- of value of m is as minimum as possible. 0 Fig.5.114. State diagram of clocked sequential circuit ‘The ae tabl forthe state diagram of Fig, 5.114 is shown in Table 5.68 areequvalentbecause the next state and the outputs same as wellasX= I and hence, gis replaced by e and the stsig col 0s spe tne wae table stow 8 Table 5.7 includes ig ue | ve Aevigned v @ "000 ° o10. a om ‘ woo | seassigned to alphabets may be any combination for ad ‘Thevaloes asi : desing vine a value should not be assigned to more than gat ‘only condition is that han one art srample 5.20. Design sequential cuit wing JK fhip-Nops fp diagram shown in Fig. 5-115. the ae ao Fig. 5.115 State diagram of sequential circuit Solution ‘The state table i given in Table 5.71. Table 5.71 State table fr state diagram (Fig. 5.115) gt! os = ae 7 ert ented genn Take 573 er exciton table fo the se diagram sig Hip top ‘Nest wate [Output] Tapa of pops Ge [oe] ¥ Pele pe tate TT+{*] 0 BREE Belt | ot eo (oe leila oli jo] o jolx xlo ae al il eua teat xe x}o | rfo}o] o lo)x}xlr}xfe| ofofa | a jr\x}o)x)olx rfafo la fxfrtatxla |x o}olo] 1 \olx|x\r}olx o}oli| 1 r|xlo\x\x|r olslto| + jolx\xlolx|i map fy Text wate z ee X=l X=0 X=L GO] Ge] 0] ee [%[o| ¥ | ¥ ofofolifrfofofo}t oO 1 Of; oO; 1fo}rjoyd 1] 0 0 1 oO} 1foj;o};ijo;}oj}o}o 0 1 ifofojrfofofofoji} o |! 1] 1) oft {ojojofjijo o 1 eee_Seavential Laie ins he Ok BOT ig. 5.117 State diagram of Mod upidown counter men eam shows the present state and next tate forX =O and X= i able 5.73 Stat table of ModS upldown counter mater Next state Present state = be [or] m |e To To To To Ton eo toto }o li}: toto ele baal Plt eal ae or lg Belem B-\go-c 1) Vian | od Monit eaale abelian Vt 3120, Neto luo: tala RW cb ("0.0 deiliio fn. ila “heck -teexitaton table for the given state diagram js given in Table 5.74, able 5.74 Excitation table forthe state table (5.73) using LK tlipop Tnpat | _ Next state “Input ofthe Fip-ops re X [@[@[e [w[ eo) ela |e tyojo} 0 jo}o|r}i|xjo|xlo |x Fig. 5.116 Logic diagram ofofi}o jolrjo}xtrji|xjo |x Fle) Pia aa es tn be al cee ‘Example 5.21 Withthehelp ofa state table and state diagram, design a MoS ih) LEA ad A Ea a Sata ‘upldown counter, tfofo|o Jolojojo\xjo|x|x |i Solution teferlcogjea |v |.0)\-0. sec dee tle ea a ofol{1] 1 Jolojo|xjijo}xjo \x RSE '0-1-2-3-4 during up counting and 4-3-2-1-O during down Pe eae Viet fn: (oc) anishialoxteselvaie adhe ide: consider Xs the input signal, which conto the drstion Pete Ra ee elo |ck Vea tle hatel ee atade lex Croat Te cic acts a an up counter for X= 0, And for X= le aes vale #sadown counter, The state diagram is shown in Fig. 5.117. Uses | al Saee am aiicuK mn counter using Jk 1B Logic diagram of Mod-s Fig. Stet Le i Kot = Q10pX+ BOX ‘he ogic diagram for the given state diagram is shown in Fig, 5.118 Frample 5.22 Design a clocked sequential ciruit using JK flip-flop forthe site diagram shown in Fig. 5.119. Fig 5.119 State diagram of clocked sequential circut baitte ore site diagram of Fi. 5.1195 showy 3 Thestat bh "in Tubes Table 5.75. Stat table forthe sate diagram State reduction ZZ wat ble rb te we 370 ng pag voile [Next state [Owpat| Input ora @[® |? [an oe | a Meal he|ee|tee alcaulilaroclien ole a [ook ono (a0, 8 Ae oyssleeeal a oe), 0 jet he fedelod Je rallaeel ‘Testes band dare notequialntbecasethe outputs are no macy : TeEY Fromihe sate able ti observed tha all he stg MS kay = fresno posit to reduce the tate tbl lier * State assignments The ste table incudes four alphabets and hence, the number of big, represent alphabets inbinry two. Theassined values forthe alga to Dis are given below. using x Assigned value = 2124 2 ole ‘The sate table forthe state diagram of Fig. 5.119 is shown in Table 5.76, iLe Table 5.76 Sate table forthe state diagram (Fig 5.119) eae ext wate on § fis ies forthe given state diagram is shown in Fig, 5.120. oA ger=? x= Yeo | Xe ‘The loge diagram for the gi e Qo | O Qo x ¥ = o fo Bas. o1)-t0) 0 0 ¢ eoih fail 0 ° 0 | 2 T 0 0 0 o al 1 i. o oO 1 & ak sl a state diagram using J-K flip-flop is given ‘neiit cronies ees 308 ample £23 Dssign aoe SPETIOE Sng A 9 2:0, Kmntork, yi a quence Pog se sea 0924495514746 a ‘Solution eer Sat garam forthe given sequence is shown in Fig 5,19, bs O_o" Fig 5.121 State diagram forthe given sequence en in Table 5.78. Table 5.79, fees te Table 5.79. Excitation table for the state table (5.78) using FX fipsop “Te sate able is 2 Table 5.78 State table fr the state diagram (Fig 5.121 Present stale ‘Next state @[a[a{[oalo lo males. 60). [ ao = 00,00, ° 1d | Goma aas, =2120) eye Oo | 2 fe 0 oa al iagram forthe given sequence is shown in el ach lee ‘log diagram forthe given sequences shown in Fig, 5.122 pl UO plieiaglhcty+|-o1 1 o fat isl 1 1 o | 2 ie eta et ee. yf. s| eso, 4 a 1 h 2) ‘The excitation able forthe given state diagram using J-K fip-op is given in a, Ne ate Tapa of he ios ax| OQ | Qo | Jo | Ko | Js | Kr | Ja | fig. 5.122 Logic diagram for the state diagram (Fig. 5.121) using LK flip-flop A Mae : OR Bample 5.24 Implement the following state diagram using ofojofx|xfifuiix} Melbie|ia.| x, | 0 4.x |oxaae o}ifxfofo}x|x]t Meeeiix | o |i | x | le 1i/o]x 1 x i/o x jo lane |o jx. |x | a] xlSolution peat ble forthe state diagram of Fig. 5.12918 given in Tabe 5 le5.80, Table 5:80, State table forthe state diagram (Fig 5.123) Fig. 5.123 State diagram Ouipu ap Ba ‘Next state Present state | Xa er @: [G1] Ge | :] 2 |G | @ | Y tporoyt{t{°{°]ofit o arom etalol ae] @ (a.| aio] % olifofofifofofofo} o tfofofafofo}ofofr] o iLilolifolojo}ifo} o ‘The logic diagram forthe given stat table usingD flip-flops shown nig, sd. (iy Design using T-FF ‘Tpeexctation able for the given site diagram using Tfip-topisgvenin (Design using D-FF Table 5.81 Table 5.81 ‘Theexcitation table forthe given state diagram using D flip-flop is given Excitation table forthe state table (5.80) using fipop Present state Input | Next stare | Output | Input of the, Di | Qo Beoots- cols Jbse-sccc-als x 0 0 0 0 o 1 i 1 1 1 lpes-c- -eccls 1 [0 f(D) 1}o o}o of}o of4 1]o o}o ofa Delo. ¥ 0 o 0 0 0 1 1 1 1 1 Sco c+ souls8. 5.123) using D flip-flop Te Okt OX D008 -rnelogic diagram fr the given state table using Mip-opis shown nig Design using S-R FF Yer Fig. 5.124 Logic diagram for tate diagram bi ‘Theexcitation table forthe given state diagram using S-R flip-flops given in Table 583 able 5.83 Excitation table forthe state able (5.81) using SR fitlon Ouiput| Input of the flip-flops oo |X ¥ | Sof Ro|Si [Ri [S[k apofo]o [i}rjo| o | olxfrfolijo ofo{1 | o jolrjo| o | oj1}r\ojolx ofr fo fo Jolijo} o | o)x|x{ojo\x 1fofo|o \1{ojo\ o | o)x\o\x|xlo 1fifo|o jr {ojo} o | o{x}ojr|x}o ofo}o|a Jojoljs} + | sojo|xjojx ofofa | a fr fa fo} a | o}r)rjojrio O}1jo o}o\o 1 of xo] 1 [ox 1yojo ojo\r 1 1[ 0 fo|x}ojr 1tilfo ojijo iL o] x{x}o jolt=O Kemp for, ot [ut m (Fig. 5.124) using Tfliptlop a cs Fig. 5.125 Logic diagram for state di cKSS ‘pe logic diagram fr te given sate able using. Fig, 5.126. iD-Nop is, toy, Fig. 5.126. Logic diagram for state diagram Fig. 5.123) using $8 pop trae ee Sp Sons achat iene oe agra forthe given Sequence is shown in Fig 5.137 on 2 ® eG) Fig, 5.127 State diagram forthe given sequencerig Beeoies _—_ L 20, a ol fe Kemap of, ee Kamp ford 1 x] 1| x ot =O Kean forJ 0:04 “The log diagram for the given sequence using J-K flip-op is shoya Fig. 5.128. 5 oe a B44 af- > Yoo ia Fig. 5.128. Logic diagram forthe state diagram (Fig. 5.127] using }K flipfop 2 LOCKOUT CONDITION ‘In Example 5.25, the clocked circuit is designed to generate the sequsse 0-42-45-+4-47-40, the states 1, 3, and 6 are unused states. If the sequence ‘generator finds itself in an unused state, the next state is unknown. It maybe Posibltatthe sequence generator go from one unused state to another vss Ase butt ever arves at a used state, The circuit is said to be locked? on of lockout, there is a need to design the ci found inan unused state, the next state shoot te, The state diagrams ofthe sequence gene condi ten seta ince elon $-r4-+7-90 withlockoutconditonsshown npg ey InFigs, 5.129 z Q ax » oo re diagrams to generate Fig.5.130 Stated 5.129, State digs iagramstogonertsthe Fo SU uence 0725-24-97 90 Sequence 0-125 457-90 wth With lockout condition loekae el snfig 5129, when te sequence generators found inan unused stati next suteisavsedstate0. When the sequence generators found inan unused sas, the sees the nearestused stain Fig. 5,130 For example, forthe unused state 1, fpenext state is 2;and forthe unused state 3, the next tates. frample 5.26 Design a sequence generator to generate the sequence 992-95-+4-97 and avoid the lockout condition using J-K flip-flops Solution ‘The state diagram to generate the sequence 0-¥2-95-94-7 while avoiding the Jockout condition using J-K flip-flops is shown in Fig. 5.131 @) ey) el ae Fig. 5.131 tate diagram to generate the sequence 0125-94-17"re ate abl forthe tate nga F.5.131) is ven ig ratle5.86 Stable forte sate diagram ig 545, Fi tion table forthe given state table is given in Table 597, £87_txcoton table forthe state table (5.06) sing pop Input of he rope =x oe eR See Srila gy eg 2 ak h-01 0105 pe topic diagram forthe given sequence using JK fip-ep i shown in 5132. oe at- Bef aL ek 2 132 Loric diagram forthe tate diagram (ig. 531) using HK pop, 5,23 SEQUENCE GENERATOR ‘Thecicuit which generates adesired sequence of bit aclockisknovinasa sequence generator. Theba generator is shown in Fig. 5.133. poeiat ectronics = re roefart desk” # SEEN LENEAIOT S35 Follow : «ry the minimum number of Flip-ops required re minimum numberof flipMlops required depeng, emi enter Toe es Max (Cy, C2 om tcegtt rg ete na de Nrareraich Gicah 5 +2. Draw the stat table as per the following procedure, “ or vig deed weve rom LSB) ane ih prices te opt Fe cas eeu in ter psnesa ce sl sein 5, Draw the state diagram from the state table {4 Prepare the excitation table onthe basis of present state, § Deo the K-map and simplify the same. Draw the logic diagram. example, suppase we have to design Sequence generstoe sequnce 100011. eqUENE® Beno gen Naber of Isin the sequence is five (C, =5) ‘Number of sin the sequence is three (Cy Max (35)S2"" sso! n=4 ‘The ste table to generate the desired sequence is given in Table 5g, the ou "Duo eng, that et, nd nex state, ie ty “Table5.88- Statetabletogeneratethe sequence 11001011 TG: [Os [Oe | State (on) ofofots ft] ey {oo MeAOA IEA \sp-14- 1-3 ofofofol}o el 0 Soe ea ag o}ifoto | «| @9 @ o o}1 0 2 (0 4 Bey 1 | 7 {aw ae 2 Fig. 5.134 State diagram (start from LSB) is assigned under the column of 1Q, are assigned as Oor I such that all the states Be the state diagram is shown in Fig. 5.134. a ees e table fe ciation span_eation table forthe state diagram (Fig. 5 fe forthe sate copa Fe 5.13) wie stop 03 fr the state diagram of Fig. 5.134 ‘is shown Min Table sg, ex oxne>|S 2,0) 0] oOgram to generate the given sequence is shown in "ie Si3s, 2 eu Fig. 5.135. Logic diagram to generate the sequence 1100101) Example 5.27 Design a sequence generator using D flip-flop to generate ty sequence 101100110. Solution "Number of Isin the sequence is five (C; =5) [Number of sin the sequence i four (C= 4) Max (4,5) <2" ssn ned Thestate able to generate the desired sequence is given in Table . 91 ‘The desired sequence (start from LSB) is assigned under the column of Qhatd evaesofQ, 0 and Qarassignedas or | such hat alte stateshae ers Fig. 5.136 State diagram for state table (Table 5.91) ‘The excitation table forthe state diagram is shown in Table 5.92, {able 5.92 Excitation table for the state diagram (Fig, 5.136) using D fliplop ee Gon gos] "|. 0° (ue oe leek ts aan Of Oot) ate Veo to | ol Lae alah atte plepeleo. |e). 0.) uri le On| soc islet ile Cj El ae ae abl Tn arr At bo. |) occlu shell tel aaUal oe tee BM el iah nla | ie A alice altel taale atin oaled SH O% |i Ovo}. tis-| oupx fro. gate Oui OOE [i Oe HT (Ojo 1-02 ea ee va bacane Visrehte Ro | ate eG oli fo fi |ololofolololel)oe) ec Kap for Py 2,0: 2100, 00. 5.24 SEQUENCE DETECTOR ‘Thesequence detectorisalogi that detectsa desi to detect a desired sequence isas follows seauence. There 1. Draw testate diagram forthe desired sequence. The procedure today te sate diagram is explained in the example given below. FESS SSS 2. Draw the state table from the state diagram. Re l ci 3. Find the required number of flip-flops. a ma 4, Draw the excitation table forthe state table the sequence 101100110 ig. 5.137 Logic diagram to generate the sa 5. Draw the K-map and simplify the same. 6. Draw the logic diagram, Example 5.28 Design a sequence detector to detect the sequence 101011. Solution ‘Thenumber of states ofa state diagram is equal to the number of bits inthe desied Sequence. Inthe given sequence, the number of bits is six and therefore, the numer ‘ofstats is six. Te state diagram for the correct sequence is shown in Fig. 5.138. The states ofthe state diagram are defined by the alphabets a,b, c dye, andj TH y dc8 oo 0 4800 when the complete correct sequence is not detected. Once the correct sequence, the ‘output becomes 1. Clockgoa, _ Distal cronies —_ ga Se Ls Oo > ; as an rO—O O~ fa s8_ Sone or core stv oy Present statea reatlshebitpe WoenTa1, Pt teathc son elit Gti denied sequences 1 1X80, ¥ mustbe 0, andthe neat Fy iu G @ Fi. 5.139 Present state b When: iscorrect(11). When X=0, the sequence is wrong. 00 0 to Fig. 5.140 then the next state isd, because the third bit ofthe sequences correct. When X's 1, the third bit is not correctly detected, but there i no needa {0 tthe initial state a, We assume that the first bit is wrong and the third bits cont meseauenceI1t-willbetratedas 11 and hence, the next stateisband ie swrenX= Fig. 5.181 20, then the next state se, because the fourth it, Ly=0. the fourth bitofthe sequences fed. When X is O, the fourth bits wrong and iy detected. W! Wand the nex state must be coma pecs the wholesouencs wrong. Fig. 5.142 Present state e when XisO, thenext tate is fand YisO, because the fithbitis correctly detected When Xis I, the next state is c. The sequence 114 willbe treated as 11 and Yis0. Fig, 5.143 Present state f ‘When Xi 1, the next state is a and Y's 1, because the lastbitof the sequences correctly detected. When X is 0, the last bit is wrong and the next state must be a and Vis 0, because the whole sequence is wrong,State table ‘The state table forthe state diagram of Fig. 51 Table 5.93 Statereduction From he statetabl, itis observed thatall he states areditcen and there i no possibility to reduce the state table. State assignment The state table shown in Table 5.93 includes six alphabey andhence, the number of bits required to represent the alphabets in binary istee, ‘The assigned values for the alphabets using 3-bits are given below. Fig. 5.148 4d ig 418 siven Table 5.93 State table for state diagram (Fig. 5.14) ‘Newt state x0 | X=1 [xco fee Cale ee > afelfo a f Variable Assigned value @ 000 ’ 001 © 010 a ou e 100 a 101 Output for X= 0 and shows the present state and the next state for input X=" is given in Table 5.94. pipes 94_ Site bl fr Ste Str 5.148 yay Feat esi sate X= Ug watt ae 2 [| @ [@, [es yt Bop efe}e fetta eTelsfefofefotr tel s |e Gieotoi| alo | os(ul ee aes eyittfofotolr lolol § |e Baral | 2] 9: | scl saaa et tfolilelelelelotsl 3 | ° | canoe fore gven Se dpa ng tiptoe me sae 9 fxon ble fo Se Tale. ang pop “pant sate [Input | Next sate | Ourat] —apat ofthe its eae * alee ee ae ae erol © lofolol o jolxtetxtets wlilitalie |0| 0/0). 0 (ata Velaeie ls de aot oo Sefer | 0 Jr eH A Va ai site| on popes lo hela tala tole Tee [po | 92 tel too| 15] agntl Be Vin Pl ath rilarilese | vos? | sa: doshastl tated sl ante aly ofolo| sfofolr) o ftlxlolx\olx Ge Hestle Ve Vaa| 01S 04 Pome fl ast ee ofrfo} 1 fololrlo jalxlxlajolx fafa} a frfofo] o \xfafeli|r|x ifofo]} 1 fofifo| o Jolxfilx|x\r rfolr {1 jofofo] + fxr folxfxhs Cee og“ o_o wl x |x| x[x alx |x [xix 0 10)DN Oi Kap for ci a ory ane ou eat Ct oO Y=2,0) Th eda fre given ate able using JK fips Fig. 5.145, ea ‘Design and implement sequence detector £20 clock sequence crcl and RS detect the sence restate diagram forthe correct sequenceis shown ints eee oF Se aoc amare Sen i cre emcee eda eral en detects the complete cre saiece he A ows Output becomes Fig 5-146. State diagram forthe corect sequence 1101011, presentstate a ineaXis,thenext stateis band Yi O, because the istbiof the desired sequence I LIFXis0, then ¥ must be O and the next state is a Fig. 5.147, Presentstate b ‘When Xi, thenextstateiscand Vis, because the second bit(11)f the sequence iscomect. When X =0, Y=0, then the next state is a, because the detected second bitofthe sequence is wrong. Cw Np Ore Fig. 5.148gt Beetones Presentstatec e next states dand Y's 0, because th When Xs the me tha 1M When Kis the thd bit of the sequence gg Pio coe Hato gotothe intial state a, We assume Pot correcyy gin he Firs bitig fecteg is wrong iergprlogto inal ite Wenn IevrconstTesequne 1¥ilbe tented ac gag Ot ome isband Yis 0 the yay Bs er Presentstated ‘When isthe next state is eand Ys, because the fourth bit oy he sence, Fig. 5.150 Presentstatee ‘When Xis0, the next states fand Yis 0, Because the fifth bits correc When Xis 1, the next state isc. The sequence 11H will be treated tly detected as 1 and 7 is0. Cait es reir u cota te hen. te sin Oo eget ee nd Ys, because the whole sequence is wrong, neste, Fig. 5.152, is $ 1 OIA RES ta 9 wetter tt hs ta pec eames hat Oder Fig. 5.153, ‘Satetable: The state table for the state diagram of Fig. 5. 153isshown in Table .96, Table 5.96 State table for state diagram (Fig. 5.153)—_— sane state table, iis ObSer¥6U tha all hey rs wis : Ee anes ea aaa me eee ee a poe een pa Ss safari n srt : — : [els [x| .. uli Tt) tle 1 5 bio Ho : WHEREEEEH = 05 +0040, me on : 100 j 101 5 I 11 hows the present state and the next state for ih “20 and X = 1is given in Table 97, "0 ‘re state able whi and X= Te and the output Fr. able 5.97, State table er Next state Present state | ao 4a TI Go| @ | 2 [ O| @ | 0 | 0 o|1 o fo 1 ° 1 0 ior state diagram (Fg, 5.153) in binary oe a} 0 oft r| 0 9 i]t 6 oft [ai] 0) | iLife ofo| « |i | she cxain ale forthe given state dagram using -R ipo sini the Table 598 rabw.90 Beinn able for state table Table 5.97) wsing Hipp Frsnrate [put | Newt tate | Output] Input of the fens Dalat x [open] oo] ¥ [5 [mo [s [mi [ ssl cee Tote] o jofofo, o [ox )o |x pole Be R ain || 0/0] 1 | Oxia wo on let (egal etineh alah. fale|> On4-| 4:0] Oe eC 1 OG ao. Neale t{ifi{o fofojo] o fo} 1 jolryele eo tiole}o filo|1} o fr] o fo |xyeis aloe] r}ofrfo ofo} o Joli }oyxioyy it ilt}i}o fofofo| o jofs oli |ely heosl tenttae| cont O; ojo] 1 Jojojr oO r{o}o}x}o x ‘. oll tjojiso 0 0 1 1} 0} 0]% ol 0 0 0 0 Holi fofolr} o fifo jolt] oly ee oft} ii ¥= 0,0. ofifo} o Jot xjryo é a Mla) ¢ |x}o{1)o iste i iagram fo he given sate able wing S- Hipp stow it ieliosloto| 1 [0 | 1 [0-111 2 aio J‘Sequential 2, and implement a sequence detector 1101 : ne, Pein D tiptoe a i gece henner seven andre umber sae forte creetsence shown. 5, ero inde tese ar defined by the alphabets, b,c. d,e,fand g The output wl 001 sing a es sarge on ne comple Cec euch cad Oe ice comin comes ees, tbo Fe 0 ig. 5.155 State diagram forthe correct sequence present State? rr impetsateiband sO Decaf fe eed eee Worry then Y mst be O and the nex sate Sig* GG SE GS Fig. 5.156 Present State b ‘When Xis0, the next states cand Yis 0, because the second bit ofthe sequenceis ‘urect, When X is 1, the next state is b, and Y is 0, because the second bit is not conectly detected, but there is no need to go to the initial state a. We assume that the first bit is wrong and the second bit is correct, 14 will be considered as | and. ‘hence, the next state is b and Y is 0. Fig: 5.154 Logic diagram for the sequence 101011) detector Qu Clock{and Ys 0, Because the third bit ory sie next ste isd ie a deme eens and 50 ree ae on he) CA, 0 » (@) wey Ca aes wm Fig. 5.158 presentstated Xi the next a erent uh Wg And he eta ay coc genset whole sequences TONE ac pt v0 Fig. 5.159 Presentstatee When isthe next satis and Yis 0, because the filth bit cometh dete 1406 wll be treated as land is {When Xs 1, the nextstateis b. The sequence ixth bit of the sea Is thenent state is g and Yis 1, because the si 5 is WrOns: |. When X is 0, the sixth bit of the sequenc Ba: Gas ae? S21 te is oF eto Fig. 5.161 state 8 7 ponents aand Ys Lesa he sti fhe seen ea Xe er XisO, the last bitis wrong and the next state must be € w vel oot detect quence O1GEOOE will be treated as O1 and is 0. 0. The Fig. 5.162 -Thestate table forthe state diagram ofFig.5.158isshowninTableS99, siatetable 5.162) Table 5.99 State table for state diagram (i le wean es Sateredution From the sae table, itis observed that allie statsareierent ‘nd there is no possibility to reduce the state table. Stateassignment The state table shown in Table 5.99 includes sevenalphabets anlhenos onumberef ts oquire a represen the alpabesiatna 5 Theasignd values forthe alphabetsusing -bisareiveninthe flowin -x= Ieand te output 10 State table for state diagram (Fig. 5.159) in bi se wiih dows the present slate and the nox sie cand X= is givenin Table Sten Quip ls--e-solg| Peee oss leo cocalpl --o->- ls flops given in Table 5.101. table for state table (Fable 5. °, oT citation table The excitation table forthe given state diagram using Df. 100) using Dflipop Table 5.101 Excitation [Present ‘Neat state Speyrren te] ao] e a]e 7 aaa ofofo ofo 0 eoubnas ad ojo} i alia ofl ecient o}1}o oft etl ear tesla tee ee o]o o }ojo}o aaa 1 0 e 1 0 + ag eld afi oh ha gate a Mapes) oft Gor hi leg pala? o}o of} 1 fo}o bee o}o o fi fojo Belch | ojo obese i at 1}o ofofo}! Bef. 0 0, fissbeeal alfa ea gt O.. |cctvelluelie a eet 12 Sin oe-Telogiediagram ert given stat table using D flip-flop isshowninky e519 eee SUMMARY SSS “sTh ierent pes of fipslops are () S-Rflip-op i) -K Nip-ep, TEAC IK hipsop, iv) T flip-flop, and (») D flip-flop. a «Prost an clear are the asynchronous inputs used 10 se the initial condo the ipo. «In $R flip-op (sing NAND gate) when $= 1, R = 1, the outputs Q and Tae Sane, Logically it snot possible. Such a state i referred as forbidden state. Tix is ome of the important limitations of S-R flip-flop. «The race-around condition is a major problem in J-K flip-flop. To resolve his problem, the J-K flip-flop is used in Master-Slave mode, + In flpfop, the output is equal t0 its input, but the outpat i delayed by he mount of clock. + The maim clock frequency that canbe applied a a CLK input of ip Tipe tdi pesto sea as Sou = ig ty eset ine of i flop 4s propagation delay time of flip-flop ‘hy = propagation of next stage decoder “an ve axed in @) Bounce elimination switch to nana Rose Meo WO Retinen se ajc cru ital eit in which he opt site wel fst aps od atte ee ati fied as (i) Serial In Serial Out, st od) Si In Seal On, Sl a Pat om a. and (v) Paallel In Parallel Ou ‘po ety Sei Out and C el O Bae ich ne nee anor eda a re se estes 3 it reiater is used multiply or divide the number by 2, ection’ got shifted out of register ee ations of shift registers ae (i) Serial-o-P ppl o-Parallel convene, sR cral converter, (it) Ring counter, (i) Johnson counter, altel at pera and detector, and (i) Dela ie ene ra er cont N lck puss. The gan fe piss ob ec ey the lock ple vied by Hea, no aay count aie othe poles obtained at Ops te feguency of the clsk pulses, «The Fee ence, it is known as divided-by-2N counter or twisted vided on counter count eightclock ples, Ani ia aaa An lock poles coo tiple counter ose Mpls, whch counts 2 clock ple oes outer ela se ah eed ie Ang cls ae Insp fhe counter reas he spent of operation, onae oent sa clocked synchronous crcl in which th utp ¥ depends Moh preset tat ofthe pss. Ii independent of reset input) vay cla locked Sequential ccm whic he up depends on he Non sat and the inputs of Hip-ops, ce diagram is a graphical representation of the state ble. The stat i ‘oy acre, with the state indicated inside the cic, Diese lines ‘een te cles indicate the tans between the aes when te ips 4-9793. 439. Design a sequence generator to generate the sequence 0-12-93-¥4-91 and ‘voi the lockout condition using J-K flip-flops. 40, Design a sequence generator to generate the sequence 101101100 using D Alip-lop 41 Den nine a sequence generator to generate the sevenee oto i clock sequence cireuit and R-S flip-flop. Multiplechoice Questions sie em oD ii tis» sly ‘hteetsr stave IK ____Seqwrntia Lege cues gg iigacnor mincing 5 aia Nand K, are respectively oe © Gand x @ Xana ge TorT @) O=10+0F e eT? @ Q=TO @ odes 9S ona ict () synchronous sequential circuit 0 it memory element (© one clock delay clement fo bt sa Mod? conte io ane 358 MUS fo adecade oot Mod-7 counter © (© pone of the Above @ bit Mod 16 Se toe =) nowt Osu 1A ee = @ 100 om sie court of es oan X © tao 6 svfotiowed by 8 Mod-S counter is ‘Mod-5 counter flowed by a Mod-2 counter we counter uses a -K flip-flop, Ifthe propagation delay of wPiins, the maximum clock frequency is equal to (&) 10 MHz @ 4 Mae wi «frequency of 1 MHz is counted using a Mod1024 ple wan with J-K fip-fop- For proper operation of the counter, the tamil propagation delay pet Tipsop sage mB ©) 50 @ 10 1K flip-flop is 1. The output does not change when a clack plied, The inputs J and Kil be respectively (©) Xando (@) Oandt 4a divide-by-78 counter can be realized by using {@) 6 Mod-13 counters (@) 13 Mod-6 counters fo) 1 Mod-I3 counter followed by 1 Mod-6 counter (@) 13 Mod-13 counters t0-tn sequential circuits, the outputs at any instant of time depend {@) only on the inputs present at that instant of time (6) on past output as well as present inputs (©) only on the past inputs (@) only on the past outputs 11 sing counter is same as (@) up-down counter (h) parallel counter (6) shift registers (d)_ none of these 12, The number of flip-flops required to build a Mod-15 counters @4 ws os @7ia esos Cc) @ © pop arse OF AINE We Segue 1, Hose many au aency by gay ac anwstage ripe com — Answers 2@ 3 Kons 60 n 2 10. © 14 8 ® 9 4 5 a @, 1 | pat” 6 | ASYNCHRONOUS SEQUENTIAL Circutts a ae Chapter Outline Ts stvorn se en boc cms bn ane aeat vveyneonous sequential cuts Ck “pape timate STS ee ices, and Hazard 1 IRODUCTION ________ 2 pret mot tsp namely combate el Te Oa cen dscselinChaperInsqenal eieeo changes from Oto 1, Z becomes 0. Otherwise, Lis 0, Realize the circuit using J-K fip flop. Solution ‘The primitive state table for the given requirement is given in Tables 6.5. Table 6.5. Primitive state tablepig eons __ ste 36 nial stable state 1 iy, both inputs ae vt the output i 0. represented as O, 0, insane at Oand J, Becomes 1, the circuit 2 and itso yisentered t0 indicate that a transition tg) om Hhe Se unstable state. f imilary, when f remains same at ares anditoupas0. Tiss Yeresented as ©, On h ya hi nd Zs becomes 1, the g sublest ci nied sctred indicat that ata a the fo fate input change fom 00010. Theuncincioys © Sm coceurasa result m eda represng then ny occu, 1, Thisiy ered get O1 to I When be circuit isin © or © and if emains same at and becomes, thecinitenersasablestate 6andits outputs O. This isrepresentedas6,0}gue Sithrow. Inthe fourth and fh rows, a uncircled 6 entered to indicate transition to © state will ccur asa result ofthe input change from 11 t 1p, vAcircledenty/andan uncirledentry can be combined to minimize the ping stale table by merge process. The outputs associated with unstable tates totheir stable states The minimized state table is given in Table 66, Table 6.6 Minimized state table ‘Next state, Output a h=00 | hel | thet! | thelo 1 oo 30 4.0 en 2 Lo a0 o1 60 a 10 30 o0 60 Since there are three rows in the merged state table, a 2-bit variable can be wet "Passigned to row 1,01 assigned to row 2, and 10 assigned to row 3. The preset oor ie endopableispivenin Table 6.7. The unstable sates asi! secording other stable stat. i Neat sale, Oupat Hh=0l | het | —anete a1,0 a ee 1.0 epee oo | wo | ao | 4, then an excitation and output table is required as given pepo ise probe 68 Table. 6.8 Excitation and output table TBD KT jon JK), UaK2), and Zan be simplified using K-maps, jon funet ‘The exci asshown in Fig. 64 fh ih ma ego] 0 [0 ooo of 5 1 nb lx] = em ed Jib YY, 1 oo] i] x oiife nbs Kami Tan iaz Fig. 6.4 Kemap for Jy, Ky, Jz, Ko, andZ hhh +hhY, ey) 2 (64) (6.5) Ke], ae EG Zen LEE +hbte ; “Using the above equations, the circuit diagram forthe given asyochronouscircut can be drawn, as shown in Fig. 6.5.Fig 6.5. Circuit diagram of Example 6.2 inputs, f, and f, and one output, Z, The circuit is required to give an order. Solution ‘The prim ive state table forthe given design requirement can be constructed s shown in Table 6.9, Table 6.9 Primitive state table ae ‘Next state, Output th=00 | i h=01 | hh=1l | hhald 1 0 3 2 2 4 2,0 3 1 . é 6 ‘ 6 a i | os Primitive te tbleshown in Table 6.9 can be minimized by merging NS 1106.38 shown in Table 6.10, — ratte and output ble is given in Table 6.11. The usin signe Table. 6.11 Present sateen state and output table _ YZ Th=01 | thet [nm [imeoo hate ee (08.0 01,0 10,1 00,0 a 01,0 ono 10,0 01,0 10.1 10.0 10 “7x ip-lop is used, then an excitation and output tables gene as shown jn Table 6.12, Table. 6.12 Excitation and output table I Ky Is Ky % n% [he00 | Wh=01 | Wh=tt | helo ma 0x0%0 | O%1%0 | 1%0%0 | OxOxt Be | oe no: (aaa aeons | too 10 xtoxo | xnixo | x0,0%0 | x00x0 “Te excitation function JK J2Kz,and Zare simplifiedusing K-maps,asshown in Fig. 66. i ih oo nh Melo 00] alo 1 ue u be fy ls nf is a u a fs Fig. 6.6 K-map for J,, Ky, Ja, Keand 26.7 Circuit diagram of Example 6.3 (68) 69) (610) (al) (612) Using theabove equations, the circuit diagram of the given asynchronousciai can be drawn, as shown in Fig. 6.7. 6.3 PULSE MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS 6.3 PULSE MODE ASYNCHRONOUS SEQUENTIAL CIRCUITS pepe asynchronous sequential circuits, the inputs and output are puss Tati its sumed that more than oe pulse wil nt arsive the inputat time, andthe duration ofthe pulses is long enough to cause state transito® and it P 5 eas uenuhsotta tre il natbe more han one sate transition oe 2 gyre sed for fundamental mode sign Proee synchronous sequen spe o28188 Pr cabe to pulse mode asynchronous sequential cicits Desgney f Designing Spronous sequential circuits requtes the following stent ae asym! a Se att ish fo, from he pen eon 1 amie eM and She of a a aad + Dexipewable st in primitive sate Ae BY MEE POE. he proses , ssi pec ine est sn = se ogni sss fing ester secon ite sae oth xn map A he 1 ees tember fos wl eed ene vareles (EAT vals) tthe rs of me + assign can oan pee ses aan ae he signed the unstable sae ary sorting othe design requirements. ene memory ckment tobe usedand bination sade oat paihesinpliedexpresionfortheexcation and otto, «sea the schematic cireut diagram nsider the design example of pulse mode asynchronous circuits. Lewset ample 64 Design an asynchronous circuit tht wil ouput only he second pus reoeved and ignore oer pulses Solution sin jock diagram ofthe asynchronous circuits shown in Fig, 68. Ithas pulse Japan one output. Aspe the given design requirement ony the second pulse verve in the pulse input should be available at the output, as shown in Fig, 69. Rules input |p = Fig. 6.8 Block diagram of asynchronous circuit alia Fig, 6.9 Timing diagram : __ The primitive state table forthe ven requirement canbe constructed, as shown in Table 6.13, is Pals inp (P) Output (2)pigita Hectromis aa Table 6.13 Primitive stat Row Le italy, he npat is (.e.P=0), the circuit is ina stable state tanga, re 4 ssorapecte 00 ae te crcalenera sabes 2 andi ey aE bine coro Ihe fro, shone speciosa wil ocr 4 el of a eld represents an unstable sta Sa ts chi cach 4 sss OR sents Dinheiro. nthe second row. an uciled Senet ii pune 3 epresentsan unstable tt. ™ Oya isin stable sate © ad the pulse input Becomes | hn Caan caabe state withouput |, Thissrepresentedas@,Iindee sepa te second pls is available tthe output "Geen ening uncle ety canbe conibinedto nina arts peep prota: Thoprinltve sate able chowninTabjea gaat samy ping ow Sandor 4 as chow i Table G12 Tha “Gicnteydecg ennai dubrarccontioed as stable el a egal ‘fied wih busable states correspond to their stable states, PLSD. sp PO Chef Zisen Table 6.14 Minimized primitive state table Next state, Output POC Fat ra 1 0.0 0 2 3,0 20 3 a0 4,1 4 5.0 1 5 ®.0 oo | Since there are five rows in the merged state table, 3-bt variables can be wed: (000 assigned to row 100 " ) (001) assigned to row 2, (010) assigned tow 3,0 ssid wae , "3 tutte 92 (100) assigned to row 5. The present statenext ste Ota ENS Table 6.15. The unstable state is assigned 000001010 lingo the stable stat, ieee able 6.15, Preset salve sate and ouput able YNZ wives Per 000, 00,0 | ono 4 oot 010.0 1.0 010 010,0 ony on 100, 0 out 100 100. 0 rpisused hen an excitation nd ouputablis generated as shown Table 6.16 Excitation and output table TK, Jaks TK Z ya¥s Pao Pat 900 | 0%0x,0%,0 | 0x0x1%0 oor | 0x1xx1,0 | 0x0%x0,0 o10 | 0xx0,0%0 | oxxO1et ou Tx xLx10 | 0x0,%0.1 100 | x0,0%0%,0 | <0,0%0%0 tation function J)K;, JaKa, JsKs, and Z can be simplified using the caps, as shown in Fig. 6.10. fig. 6.10 Kemap fork, KinKrandZ(Guy, ig saig yutions thecircuitdiagram of the gi %) sing the above equations given asynchrony ‘canbe drawn, as sown ia Fig. 6.11 Nig pAiGhhh i Fig. 6.11. Circuit diagram for Example 6.4 Example 6.5 Design as asynchronous circuit that will output only the fist pulse received whenever a control ienever a control input is asserted from LOW to HIGH sas Ay fr puiss wil be ignored. s Solution The Hock i ao ofthe asynchronous circuit is shown in Fig. 6.12. Ithas ee saad aconl input, ‘and one output. As per the given desig? @. er 4 ls received in pulse input P) is available at teow? a ntl inpatis asserted form LOW to HIGH state, and furtiti™™ Asynchvonous Sequential Grits as a al, >| uma. oe co fig. 612. Block diagram of synchronous cru a SOS ; ‘ ae onipat 2) — Fig. 6.13 Timing diagram speqinitvenntabe ert givenecceea banat iptable 6.17 Table 6.17. Primitive state table ee a row P=00 P=il 7 0,0 1 4 2 4 1 5 0 a 2 1 3 I 6 2.0 si 6 1 6.0 7 1 8 2,0 3 2 a0 7 Tntally both inputs are equal to zero (i.e. C: astable state 1, represented as ©, 0. ‘When C remains same at Q and P becomes 1, the circuit entersa stable state 2 nds ouputis 0. This is represented as @, 0 in the second row. In the firstrow, snuncrcled 2 is entered o indicate that atransition to ® state will ceurasaresalt ofthe input change from 00 to O1. The uncircled 2 represents an unstable state. Similarly, when Cbecomes | and P remains same atO, the cireut entersastable state 3 and its output is 0. This is represented as ©, O inthe third row. Inthe First ‘ow, an uncircled 3s entered to indicate that a transition to @ state will occur a8 ‘zo hep change fom 001010, The nce ens ase 0), the circuits said tobe in When the circuit sin stable state @ andthe control input (C) becomes 1. then ‘he circuit enters a stable state @ with output 1. Thisis represented as ©, 1 inthe fouth row. It indicates that the first pulses availabe atthe output. In the second *0v, an uncircled di entered toiniate that transition to ® sate will ==" rata pcg: om 1 These eenicuitisinstable state @,and Cb Whentheci OME. theciruiig se O withoutpt0. When Palso becomes 0, it will go ong, ete, - @, and Phecomes 0, the circuit enn! Mate, Calso becomes 0, it will go yrs Mable Prosetti Table 6.18 Minimized primitive state tabje % — “Next Wate, Ouipat Se Trav eeeaT | PST ao | 0,0 @1 CPT Lo 0 aS 20 | 60 [iene SIS 7 al ‘The primitive state table shown in Table 6.17 can be mini er! rows 1, 2,and 4; rows 3, 6; and rows 5, 7, and 8, as shown in Tabi engi able 6.18 eae and te corresponding unstable states are combined as the sang: TH Table 6.19 PSINS and output table ak ‘outputs associated with the unstable states correspond to their, Yin CPz00_[_CP=01 | €P=17 Te Se an Veagehdel tack cteccoita ies Read Saal ale ‘is fete patie: | ten i Pate 10,0 10,0 1,0 10 11J-K flip-flop isused, then an excitation and out tput table is generated, a shove in Table 620 Table, 6.20. Excitation and output table a TK Se Bs Z ¢ to Ratt py ox0x8 [xoxo | oxoxt | ix0xo a 0x%x1,0 Ox, «0,0 1x, 1,0 1% x10 2 x10%0 | x41x0 | x0,0x0 | x0,1x0 XLxLO | x1,x1,0 0x00 | x0,x00 Theexcitation Shomn in Fig Bratt K Ja and Zan be simplified using K-maps, asi K-map for Ky 6.14 Kemap for Jy, Ky, Jo, Key and WaCP +O% 620) c (21) PY, +CPY, (622) KyaCh+ON +P ey Z=CPHY, (6.24) sing the above equations, the circuit diagram of the given asynchronousciruit «canbe drawn, as shown in Fig. 6.15. 6.4 INCOMPLETELY SPECIFIED STATE MACHINES Insequental circuits, some ofthe states are not specified. Such sequential circuits tre known as incompletely specified state machines. In sequential circuits, notall combinations of states and inputs are possible. For example, when a machine isin asa C it will never receive a1” as input and consequently the coresponding, transition and output map may be left unspecified, as shown in Table 6.21, by & «ksh in tow C and column f= 1.Fig. 6.15. Circuit diagram som: patina of gee lapis, he expt ae ay the cg tae tener, Forexape whena mechiae|sinasiwe®, iat ‘encom, hociespontigtantion oer Bak tube ot clan te eftuspeiied os chown a ete 623 io Pt cio Table 6.22. State table Pee ‘Next tate and output = rl fa BO DA a G- BO ¢ 40 Dio (eg ree a nan taste hebehavourof te machine ms Pe nYcfisposibe nee situation, itis assumed that when the machine ounpeieditéS,he input sequences are applied sucha Wt sencountered exceptat the final step. The outputneed = ny nts yb sogene fied exwP Tre unspecified, we may specify them according to Jee ie iTable C27 i tepane SIO Teae pay lent, The states are said to be equivalent, iftheir next states ef eco cl, Now hese two ates canbecombined nds Dipped son in Table 6:23 ness Table 6.23 State table [Next state and ouput 5 PROBLEMS IN ASYNCHRONOUS CIRCUITS ric asyneronos sequential circuits have tremor problems: Cees, Race, sad Hazards 5a Cycles cesar created due tote feedback nasynchronous sequential iets, When Ce atchanges it induces a feedback transition through morethanone unstable ed suchasitatoniscalledacycle. The circuit goes through aunque sequence seaatble states because of an input change. When acycleexstsinastatetable of SKasynshronous eruit care mustbe taken to ensure that the ciculterminatesin aah stat. Otherwise, the circuit goes form one unstable stateto another until new change occurs inthe input. 65.2 Races Incase of cycles, only one feedback variable is unstable at any time, due to the change in an input variable. When two or more feedback variables change valuein response toa change in an input variable with unequal propagation delay, then a ACEcconltion exist in an asynchronous sequential circuit. Racesare of WoIY=s: critcalraces and non-critical races. Critical races should be eliminated inacircuit, whereas non-critical races may be tolerated. Gitical races Ciitical races may always go to some wrong state. It is because of differen Propagation delays, Identical circuits with different delays may £010 ‘ferent wrong states. Consider the PSINS table shown in Table 624; ; a ae___Asmetuonous Sequential tiie 481 028 10 state 0 due to a change in input, when te a qamonc 0160 ean erte ted) ea aa Dare et paar a shown 8 Fg 6 166), Patan — oo gn as stat : momentarily goes to state 1 due to char ED soup tng) | md | ne) Fe ec eran osu prance er oud) | (6 lao) on pe cna eA static-O hazard, as shown in Fig 6.16(4), 102) 0047) nan 015) ie is HOW & forthe function ¥=E(0, 1,2,6)as shown in Fig ws _|_m | iia) | Aes shownin ig 618 e617 oe oe state 3 (i. LOtg) sspondi Fame at te cit in abe Ste 38 Y= 0 amt 0 AE aie xiAy=01)and input change from 1100, Now the netstat vain, Py a rom 00 11- But det 3m unequal ropession eye soi Rms a er eres do chang pene ee cet goes sable ae ty hehe tence Ys ae 2. Therefore oraninput change tc 20 Geng eon tive switching speed of the next stat Tidy A og o M10 Se sngen tel rarest ral eiate willbe either stable tate 2 or. But both Final stats, ang 423 forthe given input change. Ths situation is called critical rae, ye MY avoided in an asynchronous circuit. tbe Fis. BE eee Fig. 6.18 Circuit diagram ee nee ways goto a correct fi the input ABC =000, the output Y= I due tothe HIGH output of AND, ‘Ano-citealice problem may always goo a.coec final sabe st af ‘When nen the input ABC changes t0 010, Yshould remain in the I state due tanston rough unstable sates. tisalso because of differen propegaiongg NN ac TEND, ge: Dvteic achangs ana plelenegEeae Comer Tale6 24a astume thatthe ccs in stable ste 3 Fe foe outflow AND; to AND gue expos td enc, Now ifthe pa te TT Asean dees Nasal | se remain in HIGH sate But, duetoan unequal propagation delay, fthe ofthe cicutaresupposedto switch from 00to 11. Again, dueto propagation dis ee aosgan v0 ilucthtbl tae ka le ve AN hen dring this brief prod, Y=Omomently. This siuaon called it and can be removed frming group facentel, shownin ig 619. Thisleads toa redundant grouping that overlapsboth AB and BC grouping. ‘The redundant term is AC and the modified circuit is shown in Fig. 6:20. Now, en the input (ABC) changes from 000 to 010, the output willremain at | state (for Poxh010 and 000 inputs) due to the HIGHT output atthe AND; gate. Yrs becomes ether 01 or 10, Therefore, the circuit will ether go to sae gj. (11) and finally reach the stable state 12. Such a situation where the cones ay stable state isreachedaftera transition through unstable statesis called anon erg) ‘race, Non-citcal races can be tolerated in an asynchronous circuit, 6.5.3 Hazards (Combinational circuits used in asynchronous sequential circuits may have unequal propagation delays, Hazard isan unwanted transient, ie. spike or glitch that occurs «due tounequal propagation delays through a combinational circuit. There are wo ‘ypesofhazards: sari hacard and dynamic hazard, as shown Fig. 6.16. AN, > > 2b) sei eee ; a Y i rd } } mt LL rey mm “es rea Cali (2) Static“ hazard (b) Statie-0 hazard (c) Dynamic hazard Fig. 6.16. Types of hazards Fig. 6.20 Logic circuit with static hazard ‘Siticharardisacondton which results in asi incomect ou es results ina single momentary incorrect 0% (Retotechangeinan input variable when the ouput is expected remain Mea Schoo ype: Sar hard and Sae-0 ias2,_Di oe. Dynamichazard = ail lich situation at the output du a. change rom, asinstatichazard ~UPof a C+BC+AB Essential hazard ie ca Ing type cireuie invepons tan inputchange, leading toatransiiontoanimprope eal, es caunotboclininsed by adding redundant ates, ane et E tial cic samme as stati a hazang 6.6 DESIGN OF HAZARD-FREE SWITCHING CIRCUtr. Static, dynamic, and essential hazards discussed in the previous sect climinated by using different procedures as discussed below. canbe 6.6.1 Static Hazards Elimination Asdincussedin the previous section, hazard is an unwanted transient. pie alchthatoecurs due tounequal propagation delays through acombinaionleey Static hazard i a condition which results in a single momentary incomeet due to change in an input variable, when the output is expected to remain ins same state. Such hazards occur whenever there exists a pair of adjacent int ‘combinations that produces the same output. ‘Therefore, to designa static hazar-free switching circuit, we need to consider alladjacent input combinations of every par of adjacent cells and ever pirat adjacent 0 cellsin the K-map ofa switching function at least one sub-cube, ‘Consider the K-map forthe function, Y(A, B, C) = 210, 2,4, 5), a8 shownia Fig, 621. The corresponding circuits for the simplified sum of products (SOP) and the product of sums (POS) expression are shown in Figs 6.22 and 623, respectively ‘The simplified sum of product (SOP) expression i (627) ___ Asynchronous Saget Greats a 483 “3 pg. 623, hen emp ABO cogs fom 00 w a ste tel ne qutput may momentarily g0 0 0 state due othe une epi je AND gates ae an remaing coma Aa once ear gt of sums (POS) extssons he sie CMA +B) Gan, peat Fig. 6.23 Implementation of POS expression inet ema goo sate soe oegtal opgaton 2 angsasiann Artest delay im" ‘spree. gwitching circuits shown in Figs 6.22 and 6,23 hazard-free, form maketh shin ace cells or ace cal, Toemove the et om a eos moe pr ae Se ee aaa el Fo ee es rcfehom ccs dotted sub-cubes. Tg een ACT +AB +BC (629) ? 2 7 gj i B lS) 2 : pt é Fig. 6.24 K-map for hazard- yet free circuit Fig. 6.25. Implementation of SOP express ‘The simplified product of sum (POS) expression is F=(4+C)(A + B)(C +B) (6.30)gem _ Diet 66.2. Dynamic Hazards Elimination so be eliminated, following the ami hazards ea a0 8 the Similar pe Dynami brn elimination, DY COVETINE Very par of | ey, PO by at least one sub-cube rey natty » = eeememmmmmmms SUMMARY —J, * nas iet e ut Sree son he rs gus the past inputs and oorpats, > oA sea of stati hi cells in the K-m wot circuit ean be clasfid into synchronous and asyney tm otter by a lock pulse. But in asynchronous sequenua cg fom one tate ext state are not comoed by a clock pulse ga aig sromycner thee isa change in input 10 the circuit tm ce « Ryntonous sequential ruts can be lsd ato wo type: yy mode an pulse mode 7 «In fundamental mode circuits, inputs and outputs are represenieq Ahern in plse mode asynchronous sequential circuits, inputs asd? 8H represented by pulses. sa « Insequetal ici, some ofthe states are not specified. Such s {ecm a incompletely specified state machines, «The asynchronous sequential circuits have three major problems, name) races, and hazards «The problem of cyeleis created due tothe feedback used inthe asynciny, sequential circuits. ns «When wo or more feedback variables change vale in response oa change p input variable, then a RACE condition exists in an asynchronous setsenty «Races are of two types: ritical races and non-critical races. Critical races shou te eliminated ina ciouit, whereas non-critical races may be tolerated +A hazard isan unwanted transient, which is created due to/an unequal propagation deta: QUE ci WY es, RENEE AIRC S| Review Questions 1 Differentiate synchronous and asynchronous sequential circuits. 2. Explain the fundamental and pulse mode asynchronous sequential cat. 2: Dessie the design procedure for asynchronous sequential circuits. 4 Baplain the probiems in asynchronous circuits. {Rebeca in asynchronous sequential cri. Tomes yc and non-criieslraces? Afferent types of hazards in asynchrous circuits? tate Mtatie-0 and static-1 hazards with waveform. 3 ie methods to eliminate static hazards in an asynchronous ce * In asynchronous sequential circuits. aeely specified state machines with ex mfronous sequential circuit. Jock syst ewe en tt ha sign 9 rit has (WO inputs, SYNC and 7 ac 2 ops ‘ sing DP pa sequent 13 Det a se incomo! ample, Give ea “KS 8 serial data tne TAO jal circuit using D flip-flops to find input signal (1). Whenever the sequence is, ofthe following found, the cat, sae 2 110 1 (O01 iD show! doynchronous sequential circuit with to i wr, forthe following specifications: “00, the output Z;Za = 00. When 1; = 0 and the J changes form 0 to Sead tos eat inputs, and, and two wazard-free asynchronous circuit for the following eats rade oy it forthe following switching ree functio f= B(0,2,4,5,8, 10,14) ai ae soe ayerChapter 7 ALGORITHMIC Star, Machines mms Chapter Outline ‘construction of ASM charts for sequent «= Basie concepts of quent ciruits « Methods of realization of ASM charts suse of ATL notation for describing sequential circuits «Realization of data and control sections from RTL code ‘importance of VHOL and its basic constructs 7.1 INTRODUCTION 7ANTRODUGHON SSS ae “any git system design canbe divided into two distinct parts. The ‘ay dim esing operations is referred to as data section and te oc {Lak with contol signals generation and supervision is referred to asthe const, section “The data section andthe control section ofa digital systemis shown Fig. 11 ‘The data section manipaates the data in the registers according tothe sens requirements, while the control logic generates properly sequenced commands the data section. aa Dat a see a tae — data data Fig.7.1. Data section and control section of a digital system The como section is. as i ro sign ‘equential circuit which generates control $8 mands for data processing by considering the status signals andextersli@pe 2a gtenime Thus, depending upon the satus and extemalinputse™h iui goes to the next state to initiate further operations go section sequence plays animportan olen pect for speciyingitshardware algorithm, rset exressing sbsrct agri and a igi design Weneod he notatonshoulbip Menting those in te a cen eet ne set ine (ASM) chats Register Transfer Language st Algorithmic 3 ALGORITHMIC STATE MACHINES ae re a eee eet cine yap ci la wc eel are rcho onhane 1a The ASM chart technique ssa sper ato, eps we ja Te Mousses Asiotane sggelgccoarse as egy which algrims ate transated. ASM chats basally co sti ns (atx seconbn ani contt o 72.1 State Box state in the control sequence is indicated by a state box. The state box is ay arin shape within which the output signals, which re generate orthe te operation which shouldbe carried out in that sate, are wnte. The nae ‘esate and the binary assignment ofthe step are written atthe upper let and Sphvcomer of the state box. Figure 7.2 shows a state Sy with binary assignment {lO which generates an output Z= 1. Tachactive edge of the clock causes a change of state from the previous sae the ext state in asynchronous sequential circuit A change inclock from to Lis ave edge for positive trigger logic, and from 1 to Vis active edge for negative theger logic. The state changes, as shown in the state diagram (Fig. 7.3), are tepresented using ASM chart state boxes (Fig. 74). Saar an z= SL on zt | - Fig. 7.2 State box of So an ee (0) Fig. 7.4 Statediagram using ASM chart Fig. 7.3 State diagram state boxigi lection wii nase £65,001). Figures 730d eas © S010) ~ or ettechangs are repesenteon the Me sus, 5 shows S2 ay ten Hite = Fig. 7.5 Representation of tate changes on the ime ay 7.2.2 Decision Box ‘A einonboxisa diamond shaped ox With 0 oF mor expat Aa pensions on he ps which ads ‘The input conition, which is tobe tested, i written inside the box. Gans MEE etron waten siete box is « Boolean expression arg en nae in Setomine which branch oak, sarsblbowa nF 768 incorporated in the ASM char ee “ i SM chartby appending to. state box, Then the present state and the condition of the input ree corresponding exit path and thus decide the next state. the “The state diagram with a condition is shown in Fig, 7.7 and its Agy ‘representation with te use of decision box is shown in Fig. 7.8, ha : xitpath Exit path v 2 Fig. 7.7. State diagram wit Fig. 7.6. Decision box condition 5_| oo s_| oo Fig. 7.8 ASM chart representation for State diagram (Fig. 7:7) __Msostne tate Maines voohanges represented On BME AKI Forint Xp res el isshownin fs = — = ch Reesprere| ots lea = sae Sate Poe wer S| 5 i [Sate at ee estes wrt S 51 fig. 79 Representation of conditional ste changes on time ai 123 Conditional Box ie yx is an oval-shaped block in the ASM. contol © "otaton which suse to the output produced during state only when a ceria input conition¢ ra Hee nenpt ato he condos box ms.alweyscame fem sae a of son Dox. Fue 10 represents coil ut musing aconitonal box me gat diagram with a conitiosl output isshowninFig.7.1 ands ASM garresentation wih the ws of decision box and onion bo shown fig, 712. From exit path of decison box ‘Conditional ‘output Fig. 7.10 Conditional box ® Fig 7.11 State diagram with Fig. 7.12 Representation of conditional conditional output output on ASM chart 7.2.4 ASM Block ‘ANASM charts constructed from an ASM block. Itisastrcturewhich represents iated with it, An ASM block has one entrance path and one or morag)_noiut te asi itputs are the functions of a sh, Unconditional Parent states ah Uno wees onion ua epee hg tenon be path sociated with an char otaionissimilart0a tate gram, ye, ae ainthe sequential circuit Each decision fo May, reformation writenalong the lines connecting the gga cae aly unconditional ouput is equivalent toa Moore yg ANAgy esr presenti Mealy machines, ine, on om in decision Boxes define Which Path) is foi aon tpenuhtroughan ASM block fomentanceroen rs OB he ink path terete i ving examples dons how an ASMchirtis avn fm pcos, Weil she realization ASM nth gon se dtp eng, isequivalen Wed thy yw an equivalent ASM ae Example 7.1. Draw an equivalent ASM chart for the tate disgram sayy Fg. 73, Ithas four states and two inputs, x andy. E xeLyel Fig. 7.13. State diagram ‘Solution ~The sequential circuit has four states with binary assignments as 00,001, 10, and, nem will be through the decision boxes correspo the transitions inthe state diagram. The ASM ig. 7.14, ut Algorithmic State See - es ay Fig. 7.14 ASM chart for Example 7.1, ample 7.2 Draw an ASM chart for a modulo-4 UP/DOWN counter having tte tate transition table as given in Table 7.1. 3 .age, isa estroics e: circuit as four sats, 00,1, 1, ance output Hence, the ASM chart ‘will contain four state boxes with a Ol, Sy = 10, and Sy = 11 Se eerany ouput writen into it andi tn ave ay condional ouput box. Tots dra the ASM char from the si sane ote counter 3500 (5). As aa aby thing ine Xvi either coat 01 (3) or state 11 (Sin UP Se IDOWN counting corespondingy. sis epresnted inte state diagram, asshown in Fig. 7.15 The complete ASM chart sas shown in Fig. 7.16, As @) F715. State diag Fig. 7.16 ASM chart Example 7.3 aft yi ‘uPA! any one ofthe four waveforms, as shown in Fig. 7.17. Develop an ASM chart for a controllable waveform generat f | hen x.¢4= 10) + wineax,x,=10) Fig. 7.17 Output waveforms satton nt abe waveform generator Eenerses one of he wavefoms, a shown ‘ep. according 0inpUIsX; Xo The block dagramof aconrlabe waveform se aon in Fig. 7.18 hast inputs X, 3 and one apa x 4 ‘Waveform Zz Generator cK Fig. 7.18 Block diagram of controllable waveform generator ‘Theperiodf first two waveforms is four clock cycles. The periods of third and fourth waveforms are two and three clock cycles, respectively, ‘The ASM chart for the waveform generator will have four states, where one sate vill correspond to one clock eycle ofthe waveform with the longest period. Foreac state, the output will be conditional onthe values of inputs present at that time. ‘The ASM chart of the controllable waveform generators shown in Fig. 7.19. Asnotceable from the waveforms, the outputis at logical Ifo the first clock ‘eleinallthe output waveforms. Hence, state Tycontains Z= 1 asthe unconditional ‘output, In the second clock cycle, the output is low in waveform 3 only and high forall others, Hence in state T;, output Z= 1 only ifX, # Xa 1. Similarly, in state T, output Z= 1 only if X,X; ‘or X;X2 = 11. Hence, the conditional output is ‘Senerated only if Xp = 1. For X,X,= 10, the fourth state isnot used! and the transition 'eads tothe initial state Ty, Otherwise, the circuit goes to state T, for which the ‘utputZ=0 (always zero), From Ts, the circuitretums to Tp sothat the waveforms ‘may be repeated.welectuonics troller, the traditional methods suitable, sale whereas age ors ag one ofthe other three methods, nh PECs 8 followings nse giscuseed, while the other two ae ston the | | sess ae i beyond the scope of hg ‘st = nal Synthesis from an ASM Chart the ASM chart resembles state diagram where cach ste ne te The state diagram canbe converted into ase able tne ge sep" rout ofthe controller. a c ‘ a belo na aren ; a voce AM a s 1 state table from the ASM chart ina suitable form (consideri 4, eamie te number of Mp DOs requed and assign ter syboa ese the type of lip-lop (Generally D Mip-ops convenient tose in ces where number of flip-flops plus inputs is more, because the input {daations of D flip-flop can be directly obtained without excitation tle) «5, Vangiapor oe simplification mth derive Rip-opinpt func toa creat output functions. 6, Draw te logic diagram (Circuit realization of ASM chan} ‘4 pn A Fig. 7.19 ASM chart for controllable waveform generator ample 7.4. Realize the ASM chart shown in Fig. 7.20 using Dfip-lops ‘The ASM chartindicates thatthe combinations of input variables (yy ni combinational Logic. foe, 7, TyandTstateassignmentsare taken as 00,01, 11, and 10 for conven 3 REALIZATION OF ASM CHARTS ‘An ASM chart proves all the information necessary ‘0 design a digital sven ‘The requirements ofthe design ofthe data section are given inside the sta cantonal boxes outputs). The control logic determined from the decisinboxs andthe state transitions, ‘Astate generators constructed from a given ASM chart. This sate generar ‘ecordsthe resent state and generates the next state. Thus, the control section din ‘wingthisstate generator follows the same procedure of designing sequential cut Asiscusedin eater chapters. However, in some cases, this method isnot suitable ‘ee lage numberof sates and inputs ee Fig, 7.20 ASM chart diferent techniques used for synthesizing the circuits are described wi ASM chants. These techniques are: J a Se aah A, Tradit aE ae ASM chart, it is observed that there are three states, one input Traitional synthesis using flip-flops and decoders ‘Wo outputs (Z, and Zp). These three states are; Sp =00, S; #01, $:= 10. Forthree sts, we need to use two flip-flops (22> 3) forthe implementation. Let ushive ‘woD flip-flops with Q, and Qy as their outputs and Dy, Dgas their inpets,os)_Doito lectrones_ ~ ‘Teste able forthe ASM char of Fi. 7.16 Wil bea gy aint ble Meng Table 7.2 State table [ea ‘Next state | % [| % | ° 0 1 ° fefebe fs : feamiler ° o i Viereaernsea lies 2] vb | ; q ThsetlesbowaTale7 2h columns ores ag andoutputs, Since wehave selected Dlip-lops, the next sta eine 8 Apo inpts. Hence, itis directly written in terms of Dy ant singe state transition does not have adecision box, state transitions of Sie {Teanown with einputx(don'ecar) Similarly Z\=1 during wag 8M {3 forboth the input conditions (x= ) im the state taba present tat is. and.x= 0, orif the present sate is S, eZee Yom the sate table, it is observed that the flip-flop inpu os ‘And the flip-flop input Dp is 1, if Oy oe it Qag ence the expressions for Dy and Dp are n=O nd 8 24+ Os et oat +2 0, Qn = 0,%= 1. And. oa 1 Or = O12 1 And Z= 1itQ,a Hence, the expressions for 2nd a (13) 22=70,0)+ 0,0 a Tielopic diagram is sbowa in Fig, 721 ation Controller Method 133 nod of synthesizing the combinationa gst ears Nlotictocanyinaoey he folio a design whichhas a direct conespond ee : ence wth the alg ex sadard mettod which canbe applied any ASM char, ‘complete ASM chart for is realizaon, 2 eae an eam an pene a ie design is pitted in a reg shod, the design is pi ular pattern of three levels of sn is ee first level contains multiplexes which determine ese coment gts tae tatonal method) panicle | (te old he present tate (similar to Tip-ops we inthe ag te pe id evel ba decodes to provide outs for enchcantul sey od onbnoal cul. sing gaint aden say (te dues 4 let For he ipo echt py ah seni produces #2 input it sate fp-p. These aie sang inp oe espn ip ap, ges he up ext ate cote wich sth outa efi te sa cf ech miler hichin tame spon alpen pene sate (ip-flop ints). input for 7.5 Implement the ASM chart shown in Fig. 720 using multiplexer contol method setation 6 Fe the ASM chart, iis observed that there ae three states, one input (X) and ‘wo outputs (2) and Z,). ‘Thethree states are: Sy 00, 5, #01, 5:10 Forthree states, we need two flip-flops (22> 3) forthe implementation. Letus taye two D lip-flops with Q, and Qy as their outputs and D,, Da as thei npats. Driving these two flip-flops for the next state generation, we need o use two ‘ltplexers, and there must two select Lines of multiplexers because the output ‘of ip-flops are connected to the select lines of multiplexers, Let us use a4: multiplexer; f/f, and are the inputs. The inputs ae selected suchthat we get the desired next state : The state table forthe implementation is shown in Table 7.3. Table 7.3 State table for multiplexer contoligi etnies poof Most diving Mip-fOp A, fo= T, 1, 0, civing flip-flop B, Io= x, = 0,1 as The out 2,=0,°0 70, +0, +0,*On re ogi diagram forthe circuit i as shown in ig. 7.29 i, letucot ps o9 Logic ake Fig. 7.22 Logic diagram ‘The ouput Zand Zs are generated inthe similar way asin Example 74 This canbe replaced by using adecoder withx,Q, and Qyassee 7.4 EXAMPLES ON ASM CHARTS: sees Obtain ASM charts for the following state transitions. () H:=0, the contol goes from state 7; to T>.Ifx= 1, generate a condition eer © It 1,thecontl goes fom 0, the contol oo T, to Tyand then to 75, If.x= 0, the Sat fom ste. Ixy = 00, go Tif xy = 01, 010 T.Ifxy= 10.80 atin Ste Machin pees tsar WOES an. tpn «=O the con! goes ‘ Weise fom T} tT fro 7 ditional operation. The ASM. a epown in FE, 7.23 Coasts ption, there are tree ithone Merl istinet *n.x= 1,the control kaa al input. Wher : euro T 10 Toand to Tsetse 75] p (=) ors Ty10T- THE ASM chanis ——-————_] it ere Ake Fig. 7.24 ASM chat (e) From the description, there are three distinct states 7}, 7 and with ‘extemal inputs rand y. When xy=00, the control goes from 7, to Ty;when ‘y= 01, control goes from T; to Ts, and when xy = 10,contrl gos from 7,10 Ty; else control goes to Ts. The ASM chart is shown in Fig. 725er he yvonne eh a stan ASM block that has three aa ample 7.7 consi © input vay ~ no ait and at = 1 ICP and Rare Hock oa isalvays 18nd Bis If (P =O and Q= I) or P= 1 ena 284 Nant ei pth 2s ake. FP Q= Vor P= 1 andy Mt Oa Peseta 1s ken ie Solution Sei cig abl a0 OPUS Fmt de Tae apa ns ta vert 4 out following any exit pall. OB ste ot wg re tating state ital sat) ring which a 4 =I hi _ represented as i Fi. 7.26 choy vie "shocking willbe followed by state Sy and two exit input conditions Input soe as indicated in Fig 7.27. Input variable Pi block will be gener! = 1, then outpor B= 1 Path ofthe checked. Fig. 7.27. Partial ASM chart Fig. 7.26. Partial ASM chart Similarly the variables Rand Q are checked and paths are specified. 'P=R=1 orif P= 0 £0, then output C= 1 and exit path 2, which i shown in Fig. 128 Fig. 7.28 Partial ASM chart 0, then output D = 1 and exit path 1. fp path I. The ASM chart is shown in Fig. 7.29. and Q= 1 then State Machines ary Fig. 7.29 ASM chant 7 Construct an ASM chart for a digital system that counts the es 3 cgi ina room. People ener the room from one door wih & fee changes a signal A from 1 to O, when the light i inte ipl Mem a second doo vith inc pel Wiha en Doha The Kat ronzed wit he clock, bu hey may say on of for moe than one clock period. saat. " Seti descrition ofthe system, itcanbe seen thatthe counts system willbane fom net states: inerement counter, deeement counte, and inhibit counter. Tesz states with their conditions are given in Table 74, Inhibit counter, Increment counter Decrement counter Here state Sp represents the condition when no one i either entering or e3¥iN& «teroom or the number of persons entering and leaving the room is same, Inevery state, by checking the conditions ofA and B the next sould bs dese for proper operation. The state diagram forthe above system sas shown inFig. 730, The system will go into increment counter state (S1) ‘nd villremain in the same state tll the condition on the siving the counter increment operation. i 7 il go ny decrement ounter ta (S) vee 1S Thes setiencnite anes open operation. The complete ASM chart willbe as shown ate) whenever A=Oand B=1 ‘put remains the same,4B=01 7.30 State diagramDigital tectonics . gases 0001219808 yg ama om 7s to Ty without any cond zconro goes from 710 To 1 EONILION. Whe se Toe conte. the control 20¢SfrOM T, to Ts, Else, ye OUtpy elo anainpo a cong we aii represented in Fig, 7.35, na _ o T;and then to om ‘The control goes from Toto Ty and then to To without any g oe a or ‘sasston Fig. 736 fig. 735. Partial state diagram 7.36 State diagram (b) The stat able is shown in Table 7.5. Table 7.5. State table Preven Sate Tipu Next Stare GTO [oe [XT YT ETF Tob, [oz o}o],o]0]/0;x]x]oloto Deena atalis | x (xu X lr.) alley ofofofolif/x|{x}oli]o ofoflilx}x{x}xfoli fo edie tial eX [iX oh (509 fehl ofi1f{ofx{x/xfo]ifo}o Aimee Se Tec! |x| Ag 81 Sp Fa gt a a BB ca sar lapel K | x.( 30. | Xe] 1 [or No ta hx | x tx |x| alo | a aati cy x (ex |x) | fag Hiiesealeat fix] ix )) x.-[x¢°|°0\] 0 en, From the state table, the equations for D4, Dg, De, and Z can be writen {rectly by ORing the corresponding minterms as: D1 = Q,0,00F + 040,02 + O,0n0c + 0,0, 0-E ep 78) 09) 740) BAS shown inDial eto states, thee flip-flops are needed forthe imp, wh Dr On Oe thet ou net 5 me rer (© Mee three D fipf10P ss eet eine i rca Oty gules nsf an Algorithmic state Machines Dice eal 1 onED) vt av (0A EY) nova imutpexers beste te En mubplner fe rete ox ule see. The np mailer 2 Indy aa a 033) Fnpats of muliplex m lexersare seletes hare jos ibe ae desired next state sch ee ast ah ‘The state table for developing a multiplexer controls sho a a in Tabs mata) Table 7.6. Satetable for developing 2 multiplexer cong) Zz Frain Tobe [Nest Sure | Input | Matipner aah, a) Qi] On| | Pa | Pu [Pe [Condition | ducer pot Mon-2 wil Be f nlolo |o;ojo| ¥F a y h 0 ojt x Iy=0 ayo o}ifo} x ngiene 5) rl os am eoa her eat] = potmar willbe nfojife fofafa z LedaAvOaF) 1folo| F 2HvO nloli{1 [oe [ofo e hao ae ais) RLaloyo 1 oy. E L= cI will be 5 E I of Mc a 1fifo E h=QaBvGak) ele ra sot a = = pice nlaftattololo] - oe Eta a reps ‘The present state drives the select lines of the multiple i z iplexer. The inputs ofthe © hn BONE) Segue snuliplexerlines are decided by the next state and the input conditions. Every lines evaluated by ANDing the next state bit to the in ions cn RE eee ;put conditions and ORing Forexample, fg of Max-1 will be In=AX¥)vOAX)vOAXY) =OvOv(o)Logic Logie 1 fig. 7.38 Logic diagram using multiplexer contro! 5 REGISTER TRANSFER LANGUAGE Inthe previous section, we discussed ASM charts as a means of describing sequential circuits which re abit complex in nature. In practice, there are far more complex digital systems, inpatcular, digital computers. In such cases, ASM chartsareno sufficient to describe the complete behaviour ofthe system, whereas the ASM chart isa convenient tool for description of the control section of the digital systems, Even though the state box of an ASM chart provides informal description ofthe data sections ike generation of output or register operations, it does not give Om to-one correspondence between the ASM chart and the hardware realization. Inorder to havea close one-to-one correspondence between the specifications and hardvare realizations, its preferred to use a notation which preserves this ‘ltonshp forthe data section swell asthe contro section. One such oo Maa edn MSI cies for digital ystems is Register Transfer Language OA referred to as Register Transfer Language (RTL). iaclern RTL operation is the transfer of information from ‘one place 10 metoe ate become very useful when the sequential system consi as ransferof data from one registro another under he coms ‘of some signals, Ta Sals-The ASM char technique for uch a system becomes Very cont Bee tok feat court. |) our a alae mo i. 729 ital system ith dat and contol secon OTATIONS. 7 RILN perationof RTL is tansferof information fom one lee toa ‘ee eo ave ben developed tat dese pinay pen, vs these notations | have been discussed. jisseton a ro Regi ‘is ster Transfer Statement used to represent the transferof contents fromregistr I oreyster2 Forexample, ZX aay speabove statment represents tha when clock ple isapple thecuren, Tea oxisterX will be transferred (copied to register Z cn eat mregrtanrewa sane use ole, if A and B are 4-bit registers containing AALS). A(2}, ALU, AIO] and = B(3) BI2), BUN) BIO) sexe atement A «B implies the following L-bit transfers, AB\¢- B3}, A(2] — BU), AU] BLL, and AO} < BIO) ‘et itreyistertransferby the statement. Xand he it registertransfer tpt atement A eB results in the implementations shown in Fig, 740-and Fg 1a.a ay say avait + transfer notation an also be Used When there ‘The register eta eS caieiy! coin mo ee Ae BI Ox Ihisequivalent 0 3 AG] < BIS} AL] © B12}, ALL) — BU}, ALO] x “These operation are performed in one clock input pulse, The con saumont Bt) xindicates concatenation, whichis joining tog. apformatin ftom different sources into a single unit, or vect ‘Ticconesponding hardware forthe above statement can be re 10 OF nfo, Presented ash in Fig. 7.42. hom, cux__cuxK cK aK eed ag) | a2 | a0 | 210) to, ul eae 1g Ta J Transfer ah a t lock ple p> tp elo fo & ap} | 402) | any | 40) L de Fig. 742. Implementation of a concatenation Shift operation \With the help of repster transfer statement, one can achieve a shift operations shown below. In the following statement, 4&0, B31) 23) the operations A[3] «= 0, A(2] < B13], ALI] — B12], and A[O] < BIL] willake place ‘Thus, the register will contain the contents of register B, shifted by -bitand logic 0 pushed in the MSB (A{3}) indicating a logical right shift operation. Tis plementation is represented in Fig. 7.43. G@kescueh Atk. ace: cuK I> v|> Yo D a} | a) | any | a0} x @ jo jo jo 2 lage zy clock pulse > clo lp 408) | ai) | any | aco) 2 FI. 743 Implementation of a shift operation ae Ce pelow FeP" Algorithmic State Mac single register operat agement, only a single rexistr operation canbe performed, oes resents rotation of register Aby -bito the right 0.24) AIS), ATH] © AL}, AIO] Att) rent © cae Alo} APT A savas pis red oF edge OE ter inp ul tate ee the imple! Jer, since we assume lthe plop within ategiser reer slave. Hence, the present values ofthe ouput ate forthe required amount of time. smentation of the above rotation statement 5 ae look pulse Fig. 744 Implementation of a rotation gical Operation Statement ie perations can also be performed on data. These operations ineude HBjon, ANDing, and ORing of the register contents, Inversion operation ‘einvert of register A gets loaded in register X using the statement xea Letusassume X and A are 3- titregisters. Then the operation is. reformed using statement (7.25) « 12s) X02] :s Here entity, is, port, and end are the keywords, Letusconsider the example of a full-adder circuit having inputs and outputs, as shown in Fig, 7.59 a his Af L+sum 2) ru oupats ape Adder F-—"C,y ip eed Fig. 759 Block diagram of flladder Twill have an. entity declaration as: str evs, acoen ie 8 Portia, 5, cin: in BIT, — Inputs; ‘Sum, c, * fim ax : ovt Bit — outputs LL ADDER; in, out, and end are the keywords. An entity deciatiog al ire pe ca FULL ADDER as three int os 4, a tity orts Sum and C id: G, nett outpPO oa aa Mode peach oss pe language that contains ei sce the Pos AB Co ate 0 pe BIT, itcan ake the vals jas the si mode out BIT sified Sgr anoer example ofan entity goons cas mutes cet show oes. Fig. 7.60. Block diagram of id eT Mux aera yx 4-1 has sx inp pcs ton Opa por VECTORs Tan a) pent language. lnthsexanpl ned clang te 21 ay Dy. Dx and, they are declared withthe lp of an aay sO isto) Inie pct ates) Brand DIB) Sand Sy signa are of mode in and type BIT. 2a eve example, its seen that theent declaration best psy sana nteas of the entity. Kony pees thenane of ieeniy andthe interface ports. 183 Architecture Body ‘intemal details of an entity are specified by an architecture body sing oneof he podlingstyles, An architecture specifies the behaviour funetionintereomections, {nthe relationship between the inputs and outputs ofan entity. Anentity canhave ‘or than one architecture, but there cannot be an architecture without an entity. ‘The syntax for architecture is as follows: sechitecture of 4s [] begin sea ih) ha “ fe ofan | oe fo Lo ea Lat {si 48) 5G) AQ) BQ) AQ) BC) Fig. 7.62 4-bit binary adder ae figure, A[3], A(2], A(1),A[0}; B13], B12}, B (1), lO) are the -bitinpats S12], S11}, 0) are the4-bit outputs; Cisinpatcary;and Cogs omputcanY: ‘Thestructural model of a 4-bit adder is as follows: : Aibrary ice; we feoe. std logic 1164.alls sstley adder 4 bit ie 2 ‘Port (A, B: in bit_vector (3 downto 0)7 an bity Sout bit vector (3 downto 0); 4) BO,ana nader_4 DEE? Trenitactare struct adler eh component 2 sales pore (ha Aa bt fend component eee signal temp + Dit! (3 downto 1) 5 begin aie iy 1 fuRL_adder port map (A(0), BOO}, C, se Px: tuldadder poet map (A(11, B(1), temp(2}, S(1), eg * + temp, im; full_adder port map (A(2), B(2), temp (2), $(2)\ tem Pej tuil adder port map (A(3), BI3)+ temp (3), 813), o6 adder_4 bi fend ot: inthe architecture body ofthe code, full adder is declared asa comy nee apis dead esabitvecer. =A ‘Inthe statement part of the architecture body, four instantiation statements re writen, Each statement corresponds toa full adder, having names Fy, FA, FA, ‘Pls.and a port map. The signal names following the port map correspond dnp ‘one with the signals in the component port Example 7.11 Write a VHDL code for a 4:1 multiplexer with an active high output using structural modeling. Solution Figure 7.63 shows the intemal diagram of a4:1 multiplexer having two slectlines 5} and Sy, four input lines Jy 1s, and output ¥. 4:1 multiplexer net ae — c_1164.al2; ores aie 1640s oe aoe ey KS ‘ip bit vector (3 down pit vector (1 downto 0); tend component INV a: an bits A_inv : owt bit); fend component ‘couponent OF; pore (A, By Cy Di An bits yf owe bit); end component signal ¥ : bit_vector (4 downto 1); signa $0_inv, St_inv: bitr ‘AND; port map (S0_inv, S1_inv, 2(0), ¥@)); AND; port map (S0_inv, 5(1), T(1), 142) + AND, port map (S(O), S1_Anv, 1(2), ¥Q))7 + AND, port map (8(0), $(1), 1(31, ¥(4) oR; port map (¥ (1), Y(2), YQ), 4), 17 INV port map (5(0), $0_inv); INV port map (3(1), S1_inv); fend struct_mux 417 Following is the VHDL code for the components used in the 4:1 multiplexer: fwesty mids 4s pert (8, B,C; dn bits Yr out Bie 1 sea nso Sechitecture Al_ADy of ANDs £8 borat _ YEA AND B AND C;igh Rectroniet ein 8 80 srt oe earn Ad_ofy Of OR 48 be ek OR B OR C OR DE entity IV $8 port (A: in bit end 2NV architecture A aig eid end 33_180; Here, the symbol ‘= is used to assign values INV of Inv is 7.8.5 Data Flow Modeling, In this type of modeling, the dataflow is expressed primarily using concurent signalassignmentstatements. The structure of the entity is notexpicitly specified inthis typeof modeling, but itis inferred from the equations, ‘Some ofthe books on VHDL. distinguish between behavioural and dataflow architectures anothers treat them together as behavioural description. The primary difference is that, one uses processes (discussed in Section 7.8.6) and the other doesnot Data flow descriptions are used in cases where the simple design equations of the circuit ar in hand. For example, the full-adder circuit discussed in Section 7.84 has the dataflow equations as Sum= A@ BOC Coy =AB+AC+ BC ‘These equations can be represented using data flow modeling, having concurest statementsas Sum =A XOR BXOR C; Ga (8 AND B) OR (A AND C) OR (B AND ©): Itsalsopossibletouse the following conditional signal assignment sateen inditaflow modeling, since they are concurrent. Whemelse statement Tnawhen-else statement, a Boolean ex al Boolean ‘iat pression combines the individ eeeuiitg VHDL’ uil-n Boolean operators, such as and, or, and not Bol opel Boolean variables othe results of comparisons using 1 (91 alo), > (reatr ro 4 . than), > = ( greater than (lesan orequa). sa when-else statements as follows xorawl ssn 1) when (Condition es expresiony, CaP of when-else statements ae given below esol ser ar when DS a ee ie wen XT Shen others? wy, wie (So > °0" and 5; = 0") ates ten © Then (8 = 1" and 8) = 11) aloe nen others: ce statement ster kind of concurrent signal atsignment statement, The tement ane yn expression and when th value matches on ofthe che esas sponding sgnal-aluctothesignal-name. Thechoicesiathewhen siti ingle valc ofthe givenexpessionoralisiof valves. Thekeyword causcan en all the probable values ofthe choices are not covered atersis sed he ynax of with-select statment is shown below. select expression select with selec’ oget_ signal & expression 1 when choices, i expression 2 whan choices, © expression 3 when others; Following examples illustrate the use of with-select statement, 1. with eelect_lines 2.with present _state s next state @ Ty when Sy S) when $1, 33 when 8:1 5; when others; Example 7.12 Writea VHDL code using dataflow modeling for 38 decoder active high outputs and an enable line. Salution Theenity fora 3:8 decoder is shown in Fig. 7.64. mtity decoder 3.8 48 Port (En, 7,5), Sp vdnbite Yor Yar Yar Ya, Ya, Yo, Yo, Yrs oak PEE3:8 decoder Table 7.7 Truth table of 3:8 decoder ag oe eas eed nase aos POE | 0 On| ae Po Popo fr fo fo Polo tafe dow) tei fsost| tor Horeca [efofate ye} eps fo.) e sedge aiel U9] Pay co es 1 py :}afaj}o}ofo}o jo }a 19] tea) secal cha] eaheh Or tol euro ifififo}ofofo fo lo tbe: (pbb hot ead Oo oe ‘Thecomplete VHDL code fora3:8 decoder using when-else statements given below asprary Lovo: Seve. std logic, Stalls out bit fend decoder 3.8 architecture dat_flovl of decoder 3 @ is ‘ignal temp : std logic vector (3 downto 0) begin temp © En & 5; 6 5, & Sor % © ‘1! when temp = "1000" ei io 611 whan temp = "1001" ot 15 11) when tenp = "1010" alae Uy seen temp = “1011” a1se Hiben temp = *1100" alee os When tomp = "1101" else eek, Neos ee sy; ee ahen ete pat Beate ae oe jeventty bas the architect body dt flow athe deca peste ate len ee i eee vl en ine together at ay inane Te as a elie doe wid is 9 BP pe in & Sa SiS ment,’ is aconeatenstion ecu statement pation opeatorin EDL, Wi tea peratr single bits, Sand Spreconeredioa ites, eps ore 7,5, = O and S,~0, temps signed the vale “0 results in dot temp =“"1000" ing the value of temp in the expression part of the when statement, check assigned the Values 0 of 1, Eight when-else statements elie By! caput signal seinable sample 7.19. Wte 38 decoder VHDIL code using witht stent, ‘of the 3:8 decoder, as shown in Table 7.7 ion sintpratve code fora3:8 decodes given below which ses with-det stent ime architecture. Instead of declaring the outputs and select inputs individually, fey aredecared as an 8-bit array and a 3-bitarray in the eny, as shown below. sntity docod 38 4a port (En : an bit $1 4m bit _vector (2 downto 0); Y 1 out bit_vector (7 downto 0) ” ‘The complete VHDL code for a 3:8 decoder with dataflow modeling using vith-eect statement is given below. Aibrary ieee; use ieee.std logic 1164.al2; entity decod 38 te Port (En : in bi S: in bit_vector (2 downto 0)7 Ys out bit_vector (7 downto 0) 04 decod'3 8; Stchitecture dat_flow 2 of decod 3.6 38 Signal templ : bit_vector (3 dewnte 017 temp © En «57 “With temp select Bissa ee + when 1000, a when "1001", $0002000" when “1011”, 110000" when "1200", ‘90100000" when 000" when when, 9000000" when others; flow 22 7.8.6 Behavioural Modeling avioual style of modeling specifies the behaviour ofan en Tre bat are executed sequentially i the specified order iy proes’ statement isa key element inthe behavioural modeling. a sateen contains asetfsequential statements which specify thefuncignae the model and not the exact structure of it, Process statement is a coneye, statement which executes in parallel with other concurrent statements anda eh ars statement asthe following syntax: iY 8 stag je (signal nane, signal name ..... signal name} proc ‘declarations begin sequential statements end process; ‘Thebwacket followed by the keyword process is referred to asthe sensitvtlin ‘ofthe process. Whenever one of the signals in the sensitivity list changes, the sequential statements inside the process body are executed in sequence ‘The process statement also has a declarative part (before the keyword begin) slong withthe statement part (in between the keywords begin and end process), similar to an architecture body. ‘The declarative part may contain one or more of the following declaration * type declarations, * variable declarations, * constant declarations, * fumetion definitions, oF * procedure definitions. 7.8.7 Sequential Statements used in Behavioural Modeling _ The soqenta statements used in behavioural modeling are: if, case, loop. email, These sequential statements can be used inside a process for The process executes whenever there is an event on signals. Algorithmic State Machines 132M ent bas the following sym: i psieson) Smee sf (comenesal statement wait oo mega tsaements sete lane li a shown ely, Mer jeanaueson 1) een. (comential statement seiigondacion 2) then ey ccaccae whit ‘The conditions are generally boolean expressions which are tested fora truor fase condition. For example, SER ie ag {la =) and (c= °2")) then y= 700007 yess ond it ‘The VHDL code for the 3:8 decoder of Example 7. telow. eae library ice ‘use ieee.std_logic 2164.a117 entity decod 3.8 isnight ectonis att os Se is e in the above code, process stat Signals En an, slgament tothe util uc peenexecues whenever tht an event on signals En or, Whe woos exeules lal the statements inside the process are executed. sequent? rspendntfwieterthreisachangeonany signal initsigh-handesprl? i ee ccrionof cacao gal pone ee (eetRcuednly wen anevertocursonasigalintherigh-handsie reso, fhe proces al the statements getexecuted and athe end ofthe proceas don values get updated. CASEstatement 'ACASE statements another type of sequential statement withthe following format signal ease (expression) 48 when (choices) > sequential statement; ten (choices) = sequential statements; ond case; ‘The VHDL code forthe 3:8 decoder of Example 7.12 using case statement is given below Labrary Leee? ‘use icee.std_logic 1164.82; entity decod 3.8 is port (2a! vector (2 downto 0); ‘Vout bit_vector (7 downto 0) fend deced 387 srohitesture behav? of decod 3.8 4 begin Process (2, 5) Degin ifm = 0" then case $ 1s When “000” = y = 00000001"; ean “O01” = y = 00000010"; Wien "010" = y < vooa00100"7 when voli” = y e "00001000"; ween "200" = ye “o0010001"7 when "201" 5 y = “00100010"; GE 0" = y © “or000100"; 411” > y © “10001000"; tee ="00000000"; ee wy melt erataterents can be Written for cach set of chokes nO 1p ements vse to iterate ToUgh ase of equenil statements, Theeare si an ems oe for’ iteration scheme: 1 tpe syntax fr the “for iteration scheme sas follows sequential ‘end loop; For example, for i in 1 to 7 loop ya) 0 ‘end Loop? 2. ‘while’ iteration scheme: ‘The syntax for the ‘while’ iteration scheme is s follows: while (expression) oop sequential statement sequential statement fend Loop For example, while (J <9) loop XG) 1G jejia ‘end Loop? 3. ‘loop’ without any iteration scheme: Tnthis form, no iteration scheme is specified. All the statements inthe oop body are repeatedly ‘executed until some other action causestheooptexit The action can be caused by exit statement, next statement, oF 8 Statement. The syntax for this statement is as given below: oop | Seauential statements ae PP teert uh statin? end loop;soa) skates Bxitstatement ; rhisisasoquetal statement, used itside 2100p. It causes the exgeugg ain nmermost op orth loop Which is specified in he sate limp “The syntax for exit statement is exit [10°P, Inen condition) dl ified, then the innermost loo Ifthe loop level isnot specified, then Pisexited. is itt in the following examples. a ul 1o0p 1 steep ae en eae) exit fend Loop 11; naif fond 109P 1 Nextstatement ‘Thisis aso a sequential statement, used inside a loop with similar syntax ey exit statement e1] [when condition}; side pleat lites epiarets. Tsseme pnalea a remingsacmensintbecuent teraonofhe pecied op, endie ee Waitstatement Inbehavioura modeling process statement is used which contains a sensitviy list. The process always suspends after executing the last sequential statement ip the process Analtemative way to suspend the execution ofa process isto use a wait statement within the process. ‘There are three basic forms of a wait statement: wait until — boolean-expressions wait for tine-expressions statement causes a process to suspend the execution ‘tian even occurs on one or more signals in group of signals, For example, wait on © Inthis case, an event on any of first iy ofthe signals executes the process with the Statement following the wait statement Wait until tn this case, the + fied it proces is suspended until the condition speci! nthe bracket is not satisfied For example, wate untéa a 5; Intis tists eh eR Occurs on signal A or B, the condition is evaluat lt sateen, an estes the execution withthe first statement followin a itsuspends again, ae pe for of walt MED, the process es at nated by a time expression, Fr example, SPEDE for atime for 20-787 ret Oe suspends for20 ns and resumes it reson oe he jn ents ving tate -nsitivity list or use wait sist Sane asm oe wal es ah xed Style of Modeling styles of modeling are used within an architecture itisrefe style of modeling. In such an architecture hody, the ene ments (a8 used in structural modeling), concurrent sigaah ts (as used in dataflow modeling), and proces statement a spears mneling) ear wari sat 789 Configurations scaremany different Waysin which the operation ofadgital circuits modeled, cca e ee sin ohitecture bodies for one entity. The VHDL language provides or explicitly associating one ofthe architecture descriptions with diff © 0; borrow e 0; O01” = difE & 1; borrow € 1; Table 7.8. Full-subtractortrth table Ta |p | Gn | Pigerence| Borrow solo" = ditt € 1; borrow & 1s peer er re 0 soni" = dist © 07 borrow & 1; cabo r 1 $100" = aitt & 14 borrow @ 0; salts Vidal aang 1 45— “101” = ditt © 05 borrow = ofifr] ° 1 a7) ru [Dito S110" 3 dift © 0; borrow = fs Se ated rates | a Gar] subacoe When “LLL” = ALLE & 1; borrow © 1s PPS jortl aoa ° aa —* Boro epee 0s 0 7.65. Block diagram of ijiti L 1 full-subtractor eaehay_£011_sub? ‘The equations for difference and borrow are: Difference =A ®B © Cin Borrow = AB + ACiq+BCin “The entity for the full-subtractor will contain A, B, and Ciqas the input ports, ‘and output difference and borrow as the output parts. The corresponding block diagram is shown in Fig. 7.65. The VHDL code for full-subtractoris given below, 1. Data flow modeling Library ieee? std_logic_1164.al1; ‘entity foll_sub de port (8; B, Ci, in bits iff, borrow : out bit fend fu12_sub; architecture cat_full_sub of full_sub is Degin és GEE & (Axor 5) xOF Ciné Petron & (not A and 8) or (not A and Cin) oF }dat_fu1_sud; thample 7.17 Write the VHDL code (structural model) fora 4bitsubtnstor ‘hari full-ubtractor designed in Example 7.14 as component. Satation |stitsubtractoris implemented using four full-subtractors, as shown in Fig, 7.66 4p ale aL a | FS ¥S FS BiG le | Yu pitt@) —Dim@) DTG) ———DHO) Fig. 7.66 4-bit subtractor using four full-subtractors ‘The entity fora 4-bit subtractor is as follows setity sub 4 bit de Port (A, B : in bit_vector (3 downto 0) Bin: an bit; Die + owt pit_vector (3 downto 0)! out bit 1p and Gx)?BAG Distt ectonies The architecture of a 4-bit subtractor will contain the dec subtneterasacomponentinthe declarative section. Thearchitecruryat” Of sing modeling is given below ; pore (hy By Gin tam RSE ‘end component; | Gignal temp ¢ bit_vector (3 downto 1); | bosin | sub port map (A(0), B10}, Bin, full_swb port map (A(1), 8 sub port map (A(2), B(2) ub port map (A(3), B(2) fend struct_sub_4 b Example 7.18 Write the VHDL code for a 3:8 decoder using 1. Data flow modeling, and 2. Behavioural modeling Solution The block diagram ofa 3:8 decoder is shown in Fig. 7.67, Yo x ae Z %, | % ne ag % sae Fig. 7.67 3:8 decoder block diagram sg Peni fs 3:8 decoder willeonsinthe declarations of teletinesant out 1. Data flow modeling library ice; use icte.std logic 1164.a11; entity dec 3 848 Port (sel : in BIT vector (2 downto 0); en: in BIT, ¥ # out BIT VECTOR (7 downto 0) ” “eed dec 3 8; factire dattiow doc of dec_3_8 is ‘ase i 00000001” when "i000", 00000010" when “1001, 90000100" when i010", 99001000" when “1011”, 90010000" when “i100”, 00100000" when “i101”, 01000000" when "1120", 10000000" when “i111”, 00000000" when others; ena dat flow deci wal modeling jece.std_logic 164.812; featity dec 3958 port (sel: im BIT. en: in SITs y + out BIT_YECTOR (7 downto 6) vector(2 dewnte 0); ve fend dec 38; architecture behav_dec of dec 38 is begin PL: process (sel, en) begin ie (ene 1") then cage sel is ‘when “000"=#ve="00000001" ‘when “001"=¥e="00000010" when “010"=9ye="00000100" when “O11”=¥e="00001000" when “100"=¥e="00010000": when “101"=9¥e="00100000"7 when “110"9¥e="01000000"7 when “111"=9¥e="10000000"7 fend case; else -__ye="00000000 (end ie;Exampl rodelin rite the VHDL code for a 4-bit comparator ye 7.19, Write PASO ng daa tg Sotati : ‘ Soltonparator wil hae 3 outputs which are (A= B).(A <8) ang cae commer nestosminig 768 440 ee t—-u=) eal abit | cote [>< (=a E oe me Fig, 7.68 +bit comparator block diagram “The following VHDL code represents a 4-bit comparator, aibrazy Lee0/ ‘one see, std logic 1164.a12; fentity omp_é Dt is port (a in BIT_VECTOR (3 downto 0} tb: dn BIT_VECTOR (3 downto 0); eq : out BiTy ‘out BIT? out BIT end cap 4 bits architectore onp_4 bit_arch of enp_4 bit is begin eg"! when (a-b) else ‘0's Jesse ‘17 when (acb) alge ‘0's Greatere=‘I’ when (a>b) else 0"; end cnp_4 bit_arch; Example 7.20. Write the VHDL. code fora positive edge-triggered D flip op. (@) withootreset and preset inputs, (©) withrese and preset inputs. Assume the delay of fipflop is 5 ns. Solution (© Te bs D ip-sop is shown in Fg, 7.69, Te rath table is shown ces fora positive ed Ege ee tiggere spe loin checking codon CLK ce ge os swing a +¥e going transition or netic eet wo having A+¥6 BO1NE m the lock, CLK’ get speaulvalen attribute of signal CLK. Hence wh ‘event is 10.8 © whenever thee referee event = True. isanevent FaKck wey ieee! Borrpo std 20gte 1164 ald? eaty Of 88 port (Din, CL; An std logic; Q, G# out ste_logic) wea v-ft? we eactare 6 (6 05ch of d EE ts pegin process (CLK) begin ae (CLK/ event and Cli (Q ein after Sas; re) BEDin after Sas; aise oeor ae0 end 4; lend process? ena 0 ff azchr (6) Thefollowing code shows aD-Aip-lop with asynchronousreset and preset inputs, as shown in Fig. 7.70. brary IEEE; fuse THEE, std_logic 1164.a12; entity Off te port (Din, reset, preset .COK Q, @ : out STD. LOGIC is . wed tes architecture D arch of bff i8 (agin at process (reset, CLK, preset) ‘begin Af(zeset = ‘1") then oe getFig. 7.70 D fip-lop with ros end architecture: and preset inputs a Example 7.21. Wrie te VHDL. code for level edge-tigered 1K fp tp (a) without reset and preset inputs, (b) with reset and preset inputs. ‘Assume the delay of flip-flop is 5 ns. Solution aibrary ieee port architecture behay_JK_FF of K_FF ie begin Process (J, K, CLX) begin A (CLK 1") case (35K) ie when “00” => 0 & Q after Sns; @ © 9 after Snsy when "01" 3.0 = 0 after Sns; @ © 1 after Snsi whan “10” => 0 & 1 after Sns; @ @ 0 after Sn when “Ii” = 9 & G after Sns; = Q after Sash fend case; sorts sate nae _ 1168.22, ©» PEeSCE, CLK: An sta toa g, G2 ont std logic): aK FE pF_arch of JK FF is Areas HC reset = ‘1/) then a a | Sua Tae eeit (preset= ‘1") then eer ga ensie (CLK= ‘1') then fend if begin Me (clk = ‘1') then cave (5 6K) de when “00” = 0 & Qafter Sns; 9 & G after Sas: when “01” > Q © Daftar Sns G © Latter Sns; when “10” = 0 © 1 after Sns; G © 0 after Sns; when “11” => 0 & G after Sns; g © Qafter Sas; ‘end JK_FF_azchi ample 7.22 Write the VHDL code for a presettable 4-bit up-down counter ‘wving an asynchronous reset input. Solution. Tesomierblckdiagramofapresetable ‘{Situp-down counter is represented in at act ES) L721, where the counter has 4-input i tt ee resetting the count,acontrolline ~ CLK Count}! ba Reset Fig. 771 40it UD counter set for loading this count synch- ‘ian. arestlineamode control inputcout cout INTEGER range 0 to 15 land spades : : begin process (cx, preset, reset, opin af (reset “1/) then leisit (cLK-'2/ and CLK’ event) then s£( preset="1) then 4 (ude*l) then alse coutecout ~ 1) end sf; ena ¢7 ond if) lend process; and architecture Example 7.23 Writea VHDL code for the function that adds two 4-bit vector ‘and a carry and returns a 5-bit sum. Solution function adsé (&,8: bit_vector(3 downto 0); carry: return bit_vector is variable Cout: bit; verlable Cin: bit := carry Yarlable Sun: bit_vector(4 downto 0) degin Toopi: for i in 0 to 3 1o0p out. += (Al) and B(4)) or (aC) and Cin) of (B(3) and Chal? A(i) xor B(3) xor Cinz Cou Parts we vi Maral pat oot 2 Nes nt maa sone en) that ads tw 40 mbit ‘Adal and Ada? ae down 00, geno a Remes c y c eeee ae ee all a SUMMARY Inthis chapter, we discussed advance methods for describing and designing the sequential citeuits. These are: (a) algorithmic state machines, (b) register transfer langage, and (c) VHDL. Algorithmic state machines ASM chars ae suitable where the system contains more number of input nd ‘Nidables. ASM notation uses three basic symbols. “We have discussed these symbols, Seicmeaning, and use in drawing ASM chars, We have lo dscssd Wo Smo) See eid Cie seioeatal Sealy deserve by ASM chars tradition tod using flip-flops and gates and multiplexer control me _Tsona sing porate loge donee be sm ate eng and design methods. *egiter transfer language ATL fotation is preferred where the control and systematically. RTL notation allows 1! sections of a system ate 10 98 carte various reset amstel—_—_—S iia Hletrnies 524 teanching (conditional transfer o, dology of data and comm We rosicel operations, and ITO sect fi $i remptementation method rave avo stuied the iP eribed by RTL code vit iat Seve wo discussed the important constructs of the Ie 8em. 3 bear aete con ore ees Fa cater VDL cpa we eek od PS the ves for simple combinational and sequential eins eseribes the ie subiypes along wit the fe VHDL co students 1 writ ememems KEY TERMS AND DEFINITIONS Stes cihmie state machines (ASM) Ics sequential cieuit, used to contol dig Algor z is outa step-by-step procedure or algorithm. vertet isa sper rotton, especial wile designing syncronous cia ASM tM eee. all he controllers are the state machines info which mg Aen a emsted, An ASM chart is basicaly composed of tee bang sige bon, decision bo, and conditional box. stare box Any state i he contol sequence is indicated by a sate box ig Siar nape whi which the ouipot signals, which are generated or te ee cation which shoud be cai oUt ta ate, ae wHten. The name ae he tnaysxignment ofthe seps ae writen at he pper left and gt corner of the site bo. Deco box It i diamond-shaped box with two oF more exit paths. express sant coniton which decide the state change. The input condition, which sw pe tends writen inside the box. Generally, the condition writen inside the box is Boolean expression thas evaluated to determine which branch (o tke Condional box Its an oval-shaped block inthe ASM notation which i seo ‘eps the ouput produced during a sae, only when a certain input condonis ‘ane. Hence, teint path othe conditional box must alvays come from ne ef te eit pts of decison box. ASM block The ASM char is consructed from an ASM block, An ASM blockisa Satre whch represents one state. An ASM block has one entrance path and fe x or ex pats RTL RT otaon i prefered where the contol and data sections of system a toe designed systematically, I allows us to describe various register anslee ‘pecans, lopel operations, and branching (conditional transfer operation) _NBDL: tis. hardware description language which is used to deseribe the stectae behaviour of a digital system. VHDL stands for VHSIC Hardware Description = mete VISIC in turn stands for Very High Speed Integrated Cres symbols used in drawing an ASM chart IM char ofa digital syem ape various 9 tations of 10k timing andthe ASM chan tne har with sitabie ‘of a neat diagram, explain the difference betwee State box and a conditional box the output ie tld eet saris ain os? Ein Fant pis ofa ASM chat tht chek he cote s ston ales, Ay Band: ot tce i ale ca 8 he Cn ma oA ac ition of an ASM chart crplmenation of ah ASM chr coins tee paps as jon of the multiple ir eee Api be the configuration ofthe mulplexer used? How many maples na eee orth cick? tha suitable example ‘ will {paw an ASM chart for 2 modulo-6 counter witha rest apt ‘paw an ASM chat forthe following description, The cc hs heap Matables (A, B,C, four outputs (WX, YZ), and two ext paths, Foetis rei, output Z is always I, and Ws 1 ifand only fA and bah ae | eee Land A=, then Y= 1, and exit path 1 is taken, IC 2 1and exit path 2 is taken, 4 Daw an ASM chart of a sequence detector which detects the sequence 110. ‘The ouput Z becomes 1 along with the third correct bit ofthe sequence. 4 Draw an ASM chart for the circuit shown in Fig. 7.72. (uaa a> >, 2 a! Fig. 7.72 5.Druw an ASM chart and design a circuit using D ‘The circuit has a control input X, clock, and o ey ig ege ofthe clock the coe of BA changes fon 00 and repeats. If X = 0, the circuit hols the present Ha S.Daign a synchronous controler having he flowing ASM ba ewa 2 Fi 7.73) ‘using D flip-flops and suitable gates- u Sipps ae Aand B.1fX= 1, on arom 00 301-10sag) DotaHectronies Fig. 7.73 ASM chart Register transfer language 1. Explain the RTL notation used for register transfer operation, example 2 Explain the unconditional and conditional branch statements in RTL. notation, 3: List various declarative statements used in RTL, 4 Explain with a suitable example, the RTL notations used for the logical ‘operation on register contents, 5. Explain how to gt shifting and rotation operations on the register contents in RTL notation Problems |. Show the hardware implementation of the following statements in RTL notations: @rexva 80, 1), C121, C13) @z=y Dea _—ASsumme al the registers 1 be 4-bit with a suitable am for system with 2-5 ro "tien, om the following Sequence shovld ues Ye loaded into A-register. Ifthe data on ype Ind be complemented and sued oun in AES ied o Roope ted and red in Caspr ae a a 8 inca ws on Zines. c ig phees On iagram and hardware realization ore ting RT ron a cam_1 ee et me Lata], Bia), e121 ea #12) surpues: 212] eet A.B na 6 ave ser Fda secon sod cong, pees eee XC 4808 po seqvENce ‘ope igram of conan dais sited yee ‘oe in wc ad bens cnp oa fae Lecxyd abes (a, (1, 3) B7e1bex9d 30) Fee a for ts Toulowing Gsacigtie: Wan he conte eceives the “ta_ou” signal fom te paces, it es ‘ied onthe WO bus data lines, These four bits forma BCD igh waka Sipe on 7-segment display unit Silay, when te cononr cena ‘the “data-in” signal from the processor, the status of the four switches within ‘the controller is sent to the processor via the same four lines. wot fat in in brief the three modeling styles in VHDL. examples, explain the conditional signal assignments in VHDL. brief the following sequential statements in VDL. velse (b) case-when (© forloop (© Next 9 Wait the various classes and types of data objects in VHDL? rious VHDL operators. Of process statement in VHDL and its importance, ‘instantiation’ in VHDL? Explain wih e suitable examris a ey des for the following combinational ci | ver ip tiane es elem cl 3 eenireeepeereairradipieata ee ey tien wc ooh . PROGRAMMABLE Logic A Ee ie PAN are ee | Devices Ore as Gna lta ———— Chapter Outline es of PLA PAL, and GAL «2286 ton of various combinational and sequent ccuts ui + imparrnabl logic devices 0 reece evar doves ke FPGA CPL, a Ac 1 INTRODUCTION elogic devices area group of integrated circuits that canbe configured [pefo logic functions The tetm programmable means thatthe function nay be od aferthe chip has been manufactured. Asweknowitsalays paseo ‘Tres any combinational logic function in sum-of-produets form, Programmable fp devies provide us the facility to create these sum and product terms with he hnlpof AND and OR matrices. PLDICs come under the LSI (Large Scale Integration) category. PLD designs picly have lesser power consumption, fewer IC count, and are more reliable tan discrete logic designs. There are several types of PLD ICs from diferent ‘exdors. Generally, PLDs may be classified depending upon the programmability cftbe AND and OR arrays. PLDs with programmable AND and fixed OR arays aecaled Programmable Arrays Logic (PAL), PLDs with programmable AND andOR arays are called Programmable Logic Array (PLA). This chapter covers PLA,PAL, Generic Array Logic (GAL), Complex Programmable Logic Device (CPLD), and Field Programmable Gate Arrays (FPGAS). {.2 PROGRAMMABLE LOGIC ARRAY Hstrcally, the frst PLDs were PLAS. A programmable gic aay deviceconii "ara of AND and OR functions whose configurations on byteernent complex combinational s PLA susedto implement comp uit InVLg roe epcame ries he spac reuiremen. Several (Slssin, LAS enti p-fops ona leo8 cip, ence it an aso cae ed fo Sequential applications 8.21 Block diagram of PLA fixed architecture logic device with programmable Ap Meee dupa of PLA town NF 8 ND andog et ai Input AND | oe oe LT cratttm) qe oR; in matrix -}-+] Non-inv ras dee Z (Sum fms) Fig. 8.1. Block diagram of PLA “The block diagram of PLA, shown in Fig. 8.1, has input buffers, AND gales aay (matrix), OR gates array (matrix) invertinon-invert matrix, and output buffers. It has M inputs (Jy through Zy ,) and N outputs (Op through Oy 1). 'An AND gate matrix produces K product terms (Po through Px_)and an OR gale matix produces N min terms (Spthrough Sy). Such a PLA can be described san (MXN) PLA with K product terms. In general, Kis far less than the number ‘of minterms (2"), unlike in case of PROM. 4 4 a Fis: 82. PLAwith 3 inputs, 3 outputs, and 6 product terms Rosana Ls be Do Hip. Tepresentation best > all PLA withthe np ic AND as anaes 32st ynected to both a true IND gets com ‘and a compler se yneted 1 cach input of OR ees through fle The ww < couay areindicatedby X's. Thedevice programmed ii aes rparonceded and removing thee since they weal wpe onto onstruction i similarin both AND and OR ary. beans. Te Se ment in PLA can be implemented withthe lp fina THD: as ree array,inverting/non-inveting mati, and output bate, i! ater. pba are provided atthe input side tao ating thence whch +e othinverteda wellasnn-ved gua ecu, terion Procter somected in series with all the: bhePLA, the required product Fig. 8.6 AND matrix Givenbelow isthe equation foreach productterm. bY "sto be intact. Re = ToT liesORmatrix rap outputs are generated by ORIN the desired product el i Som terms are formed with the OR matin. sor Logic is shown in Fig. 8.7. 8 Forming terms, The | the sum terms Ne OR mat bing Resistor Transist Pe Prod Product tems) PSs Fig. 8.7 OR matrix ‘From Fig. 87, itcan be seen that if none of the fuse links in the emiter of transistor is blown off, then the sum term S) is given by the equation y= Pot Pi + Pan + Prt 62) Whenever afuse link is removed, the particular product term will not appear inthe sum term, ‘Thus, the OR aay is programmed by fusing the unwanted links, Invert/non-invert matrix: ‘Theinvervnon invertmatrix isa buffer which isused for setting the outputto activ low or actve-high, as shown in Fig. 8.8. This is configured with the fusible ink ‘Provided actos the inverter or atthe input ofthe XOR gate. le itis provided atthe ouput sia orci let inceae Ht Oa pe utputean be 1 POE, OPEN callin ee ME wal er oeenen rota oe i | Enable o— 8.9 Output buffer ee vapteenting ork iy wed for implementing combinational logic circuits in ero sei ce use AND, OR and nents Sige MA a I WAND and OR array, its beneficial o minimize he gen leg mab nimmum SOP form using K-map or Quine-MeCuskey mt nan ch athe followed implement hisminiman SOP orm nn al 3 pepe a PLA program abe format indicating inputs, prot tems sd ts + Sefeteinpt connections of AND matrs to genera theroied pot ses. +, Hub input connections of OR mattis to generat the requied apt (um terms 4. Mak the connections required for invert now-invert mati fr seting x seve high or ative low output 5. Program the PLA with the help of @ PLA program abl, ample 8.1. Implement a full-adder circuit using PLA having thee inpus, ‘gh product terms, and two outputs. ‘Sation Teint table of a full-adder circuit i given in Table 8.1.pjtatlectronks Fig. 8.11 Programmed PLA for Example 8.1 ‘22 Implement the following output functions using a sitable PLA. (A,B. C,D)= 2.7.8.9, 11,15) From the tat Presented :m (3, 5. 6, 7) 18.3) ne Kt forthe outputs Sand Coq are given in Fig. 8.10 and the, : vk Gaia ete fr Cu $= ABC, + ABC, + ABC, + ABCin (8S ; free to trou 0s canbe son tht here even nt deg een a popaiulicment ln Tiaeea oo renee anf opie es a Sa ed sels. Te second col specie th ip te (ae 2) iain Tose OND ane al oe ro id ealimn species he comeon hi Se afar ei Loge aca ee ieee ec en at a teaan pene ornon focanmannagia CE ee ean ae re cecee areata Table 8.2 PLA program table for Example 8.1 PyA. B.C, D)= Em03. 4, 5.7, 10,14, 15) F(A, B, CD) = Em(1, 5.7, 11 15) soltion ‘ick diagram forthe above multiple output systems shown nig 8.12 ‘hile implement ng a combinational circuit using PLA, firs there isa need to one funtion in sum of products form. This decides the required sizeof PLA and far tsusedto getthe PLA program able. Even fhughK-maps provide an optimum minimization 4 vote function, while implementing the functions Looe ‘sagPLA, we musttry to find the common product ee . esamongtheK-maps ofthe outputs.Thisallows © wea twtoshare the product terms and thus reduces the | D \—-r, ‘umber of AND gates required. Hence, while Fig. 8.12 Block diagram for 8.11 shows the dias Hi rms: Y gram of a (3 x 2) PLA with 8 product let Inputs Ga ning the minterms for PLA implementation, the ican aN a Tc, = ce ‘ppcach i slightly different than implementing multiple utp stem 2 oa ‘wing AND-OR gates. \ ABC 0 1 0 1 3 Figure 8.13 shows the K-maps for F, Fz, Fs and gives their SOP forms having 2 ; see : ‘minimum number of distinct product terms. 2. el Pala 1 - 4 1 1 x 1 _ 5S 1 1 = - ¢: 4 Baie ttl Spelt 4.1) 2 f Tpig econ 536_ F apc + ACD +BCD+ACD a BL er patina foes (49¢2) ELA wih enven proioet esa eae = a Fete eau tll cel ded a | ee 4 fo) ala ont 5 a ACD 5 1 ‘ ‘ ‘ if Dede fomshet® taly-niuat]aeeoutaaealan) | = bebe Figure 8.14 shows the diagram of a (3 x2) PLA with seven produet tems programmed according to Table 8:3 BIS Go we ae a si ls ig Logic Design using PLA al sequen se for implementing sequent cruise eh ‘The design methodology for sequential circuit xs macliney in Chapter 5. Inthe complete design, PL uit remaing national circuits required to drive the fipow no ‘of asequential circuit using PLA can be ‘pflop input, Tepresented as 38 combi eet ram et ook ae com i Ae) a fig. 8.15 Block diagram of sequential circuit design using PLA and DFFs 18.3. Design a synchronous sequential circuit for the state diagram can Fig 8.16 and implement it using D flipflops and a suitable PLA. & on Fig. 8.16 State diagram for Example 83rae nate oT Heth FE ipa a Qn [Gc |% | Po | Pe | z 0 re tt |e fal 1 | 6.) (0.1 tol Out a 0 |e | 0 |) som eat aa 1 oe] 01] 1 abe |e eat o 1 of BS iO) cei eas Lea 1 1 | 0t0e|ot | Oe taaa ° 1 | O0)[0 | ae oodles 1 on 6 0 a ee o pt | a |. lee 1 Food, Deals Dork Oe tee eS anf lig | o | 04] 0 |0. | Caan x jo fofo]ojo]o] o x jo fofo jofolo] a Table a5 Facition ble for Example 8.3 Figure 8.17 shows the K-maps for the inputs Da, Dy, Deand the output Z, an gives their SOP forms having a minimum number of distinct product terms. Oe 0,0) 0 ocr 00 u 0 0 0 0 teaser ceca thas . Dp, De, and the output Z are: (8.10) peas eroleled 1) pie nok ¥ + Orne + 2rOu ¥ 12) bs ax+ jOcK + Qx0v0cX + QnOvDeX (8.13) 120s 4,13indicate that there are nine distinet products 0,81)" Daa and Z. Hence, we need touse a(44)PLA with 0 aX 6 ojo|-jo | 00x 7 O70 da lee ected tena oa | ‘D0sOe X 8 O:.) b bethalOsoteeepsaelnsral: © OO | 9 ripe Feta) pthc) dS i mer} Cee | Figue8.18 shows the diagram of a (4x4) PLA with nine product term: Maummed according to Table 8.6 with D flip-flops. 3 PROGRAMMABLE ARRAY LOGIC array logic (PAL) devices are those PLDs which are very Peer PALS, like PLAS, consist ofanaray of ANT PLA and PAL devices fates. The major difference byron Opa aly Op gates 2 ‘Gexible as the PLAFig. 6.18 Circuit implementation of Example 8.3 18.3.1 Block Diagram of PAL PAL isa typeof fixed architecture logic device with programmable AND gates and fixed OR gates. The block diagram of PAL is as shown in Fig. 8.19. | fr Be _ Programmable Logic Devices gay sun ype Nvohere M represent themamber of ame - = San theme leer tales he pean ie te fons of the following: ae eee Oi eign ours righ nce to¥ om ct cba red out is seg aed 1S vee amnable Po rsa aL with inns nd sere us By 2), od) te arias ssp ecg (b)-( 2001 op HO PAL, the registered ouput PAL andthe Fave AL, the apt put PAL. respectively eo red OUP rei oer il Ll Fig. 8.19 Block diagram of PAL The block ‘ ee, ‘of PAL, shown in Fig. 8.19, has input buffers, AND gales GPR Bie my, Hina (trough fy.) and outputs cates the programmed connect Buc am sction between an input signal and the ‘The programmed connections are made via EPROM cells oF technology.(© EX-OR Registered Otpu PAL Fig, 8.20. Types of PAL 8.3.2 Registered Output PAL Registered ouput PALs ave flip-flops that store the output. They also have an orp sate bufer. Figure. 20(d) shows the arrangement of aregstered output PAL. The flip-flop ouput is made available as an input to the AND aay to be tsedin the aditional product terms. These feedbacks are important for creating thenent stat logic state machine outputs, counter shifters, etc. The clock fr the fipop is fom «dedicated pin. The typical requirement of feedback is inthe fip-fop input function expression. For example, Dy=Q, +05 Dp= O40 ena ‘getting driven by the product terms in which the feedback is pees Q, and Op. The use of registered output PALs will be demonstrated in ae ‘sequential logic design using PAL. sae also available with XOR excitat ae ation inpats tothe output flip-flop, a wn in Fig. 8.20(e). This allows logic reduction when the flip-flop excitation functions are simply realized using XORs. -3 Configurable PAL -PALshave much more flexibility inthe output arrangement. In uch arrangement is referred to as a programmable macrocell which pene by the state of configuration bits. Figure 8.21 ‘widely used PAL: 22V10. ese ree Re A) og | cl aloes Li Fig. 8.21. 22V10 macrocell + sigur bis allow the ‘macrocell input (output of OR gate) to either be | ganas te) © the output buffer. The polarity of macrocell outputs - Bewuble “Toe output polarity selection enables the software toperformlogic _ ein onan expression and its complement and select one of the logic. _ tepaeelasoallows the feedback tobe used asan input to the logic aray. squenckcanbe directed from the register or 1/0 buffer, depending on whether .door combinational, An output enable product term can be ing the tri-state output enable pin. Table 8.7 shows the fesglis egistere for control ‘Vl0merocell configuration table. Table 8.7 22V10 macrocell configuration table acs Description a Registered and active low Registered and active high Combinational and active low ‘Combinational and active high 0 1 0 1 ae isan example of configurable PAL with 22 inputs, 10 outputs: and Product terms per OR gate from 8 to 16. 16 Con by ha combinational Logic Design using PALS 7 1s form need | tobe “Signing with PAL, the fumetion in its sum of prod eft cachsesion Sine the OR aay sfx, enmbef, cannot be changed, Hence if the number of proc omesail ect ee aca. spore then tay be necessary Fr the sections to imply any function Ta unlike the PLAS. aprxluct erm cannot be share fanction. In cormore OR gates 1.4-output combinational circuit has the foll Brample 8.4 A3-inpet ami implement the ctcut using # suitable PAL ‘Atx,y,2)= Dal, 2, 4,6) Bias) = Em(0, 13,67) bx, 2) =D, 24,657) Dix, y,2)=2m(1,2,3,5.7) Solution AE K-maps for outputs A, B, Cand D ate given in Fig, 8.22, Men Booey among ie 8 ou Kea for ouputs C ‘K-amap for outputs D Fig. 8.22 Kemaps for A, B, C, and D etx itxytyz Dect ty From the expression of output C (8.16) and output A (8.14), Canta (6.14) (8.15) (8.16) (8.17) From equations 8.14, 8.15, 8.16, and 8.17, itcan be seen that there are 3 inputs outputs, and a maximum of 3 product terms per OR gate. Hence, a4 x4 PALis ‘The PAL program ‘able shown in Table 8.8 contains three columns specifVilg ‘inputs and outputs. In this example, the input column ab protuct terms (n0), Contains A, since the feedback is used for one AND gate input. ‘equited with programmable inpuv/output so as to allow us the use of one output ‘iction (A) in the other output function (C) with feedback. —PraMNe Lege Dee | a Ty i = b z= [at . isl ieeatbaoa eS = want palo bia oy | te oe [so ea] eee ae ie fabs ele 8 Romie ihe Canta 3 rosacea a letalicy n me le lAlwacilaaee eeaEers, : pores a ee sper Table 88. rd. ‘ems 2 3 # Foe oe rigue $23 showsthe 44 PAL with 3 produc terms perOR gate progan 4a c All fest (atvays=0) D sx Fase inact Fuseblown pad Fig. 8.23 Programmed PAL for Example 8.4 Logic Design using PAL outputs and feedback from outpttoinputcan bese lovic circuits. These PALS can be used forpfs 4+ 229 s me Te PAL ch 13 s+ D002 20012. + 20.0, 2 ae | ils The PALE wilh wr any a «1821, jteanbe a erent tangy | geBOE J 400 821 kunnen a Me innate ag i spam of 13 Prodoe tems. Hence, we gee wes ‘eee eaten they at bled ese ouput ny gy pe eset maxi output ‘outputs have etralinpu nd ite contol cabo, ed pa gel sive feeds Mmpete sequential circuit can be fit into it without am ‘< hardware. fuample 85 Design ait Gry cole counter Sing tbe PAL, do ‘Show the eoded logic diagram of the device. @-O-O-O-O-O-O [@ [To [es] o [oe | taleOs|toMcaue] Oates ee | 046 (it 1 oto {gh\ ay ean, ea ofofr}olofo]y is Ot 1 eto iaiel Fig. 8.25 K-maps for Do, Dy, Dz,and Dy HE palbicdodlcweltegia teh ‘ThePAL program table shown in Table 8.10 contains three columns, specifying s}o oil btAoU cioal foal fy pews ina [i]! ofifofofolile items (20), inputs, and output PAA Vy) 1] f0:] eo 2a) teagan i : a 1y}o T nae 0 w {a sletaliea} ce acl ited bales idl eos ae lee afi ae etree ata bia ene Nec cee sf teaver go dare (ten ag wef 1}o}ofo}ijoj}o ae ofojo}of}ojoljo ‘The K-maps for Dp, Dj, D>, and D, are shown in Fig, 8.25. v= 010s + 0101+ 0,0,0, P1010, +0104 2,0,0,____Pesanaate be seen that there ate 4 ou ips8.18t08.21,itea ay vec puts (Qs 10-04) which ate Dfipsop ouput ree 0 me OR ane Hens ween = Pipuisandaset of four D flip flopsor wecanscletateneae tt pati wih nese D i foe aaxaPAL ee et a thoPAL POEM TEENIE 826 shot rable 8) cording to the table. isthe PAL diag Se gsi wccorins gram, | aa. RRAY LOGIC DEVICES: a0: : DPy= BGO,+9 devices or GAL devices iets eae aR yr tpt state similar oa PAL device The ouput sage 2) SEO a accel (OLMO Ky Late: Heong eestoatten theeatate output buffers. GAL devicesare elect dennis omarion A lesricallyersable PLDs gDshie. they can programmed when they are connected on acicuithoard jas Architecture of GALTOVE i deesanaveuptn 20;npt (homens cierto aghast! nege inguin Ct hcaaas fej andthe producers grraed from ives tsinpastoieOLMC dee pee product erms are generated rom he inputs fregeroupus ikea PAL-deviee. re eur =! Nie frit) ‘lays ouTpuT ourPUTS: Fig. 8.27 GAL16V8 internal diagram ale -—=—S—“‘ i ie ST ee oo ‘The OLMC. as sho PAL, the output polarity of G P- topamax OR a. OLMC. The wo contol inp 4A Ac ctl pamper he OL MC an bec with the help © registered function. - seem ae sve ae Teetback 0m the regis i ae =i fis | x) From ND] OR) ‘Mux cate __{_] % foamy Cock from rom previous previous stage stage output (m) m) Fig, 8.28 GAL 16V8 output logic macrocell 8.5 CLASSIFICATION OF PLDs ‘There are various circuit technologies for building and actually programming a PLD. They are based upon the type of device used for programming (like BIT, ‘diode, or CMOS). Based upon these devices, the PLDs can be classified as + Bipolar PLD circuits * CMOS PLD circuits Bipolar PLD circuits As discussed eater, transistors present at devices used these bi the AND-OR arrays have bipolur elements like diodes 0 the row-column junction in a PLA. Earlier, PLA and PAL Polar circuits, Such a bipolar PLD is manufactured with all ___ Programmable Logic Devic ble linkin series witheach. By. atiny fust itn elect an individual inkand by apply yeti ean oot, ss ese biPo eg ine ™ prying speci nghigh voltage, «PLDs hid reliability problems. These problem age oe reliable fusible inks in recent bipolar PLD crus, instead of dod an 1-chatel taser wi cir mjacedateach nersectontetwecnaninptacgs see comme inCMOS PLD, the programmable ee | ett rm mable devices, the links connection removed | Fen onP petal mask pater generated by the manta In | nie a Fe vices either floating gate pogrammingtechnslony FE ory cel contol the ite ofeach onnecton ese aTA0 CMOS PLD circuits are: $e ammable Logic Deviees (EPLD) se eal Programmable Lopc Devices (EEPLD) tt prrammtable Logic Devices (CPLD) Cee army Doce FC 4g COMPLEX PROGRAMMABLE LOGIC DEVICES logic devices are basically LSI devices which are suitable in cases aj designhas larger mumber of nputs andoutpts When the number st tputs still higher than the capacity of existing PLDs itisnecessary atte density. IF the PLDs are simply made larger in terms of inputs, Fe ey tose oer ae reuece aa si ie Atthe same time, this solution does not make any costefective use ‘fepea Hence instead of increasing the inputs, outputs and AND tems, its {ter tove multiple PLDs structure having programmable connectivity ‘Cpls Programmable Logic Devices (CPLDs) ae originated from hisidea (™Disacollecton of individual PLDs on a single chip, with a programmable ‘mamtion structure that allows the PLDs to get connected asthe user wants. fare 8.29 shows the general architecture of a CPLD with inpuvoutput blocks, “ADbocks, nd programmable interconnect. £——— Hnpuvoutpat ‘blockeon urs ditferinterms of individual PLDs, py manuf nnect. In thischapter, Xilinx 9500 gers coups froma matlt sand programmable = discussed: (C9500 cPLD Family number of external input-output (YO) pie pata as function block (FB) by Xiling> 18.6.1 Xilinx X 9500 CPLD family fer in vrs of the of internal PLDS ( 8.11 the devics The XC devices whi snd the numbe Asshown it umber of macroeels _soding vo their pack Ps ete found rom Xilinx data book 1d Macrocells in Xilinx XC 9500 Table 8.11 [Iz Part Number m | 2 - . Bo ete rocells 2 Pe. ee 288 Internal architecture Figwe8.30isablock agramoftheintea architects of XC9500 family CPLD, Figen cane used asan ipl output or abiietionl pin contin Ee rogranuing. ome ofthe pins shown al the boom) ex alse toa cl purposes ike global clocks (GCX), global seUreset (GSR) and slob thre state controls (GTS). “Te function blocks shown in te block diagram receives 36 signa from he switch nat, The number of funtion blocks varies according tothe specific device (minimum 2is XC 9536 to maximum 16 in XC 95288). ‘The switch matrix reeives 18 inputs from the macrocells within the FBs and the remaining inputs from exteral VO pins. The 18 outputs from each FBs elo set connected o external /O pins through the switch matrix. [ace wo 1 ) 36 oa Ww ial eee wo — he | nee w— eel we—_ i vo ‘Switch wr} bets ‘matrix vox }—| 36 worgck +p 18, lock 2 vorGsrg_}-¥) 18 (18 Macroeel) loarse Fig. 8.30 Intemal architecture of XC 9500 family CPLOS : | Programmable Logic Devas a ckarchitecture een C38 HOw NFB Th jos on AND matrix (programmable ture i similar 8 containing © Programmable AND array), OR matt Se oeactr cae ee as oat cen [Bscrose | z m axsmabe| Product 1] AE TeSvick an | tem 4 ie our & oa ea 7 ror a c= ie Fig 8.31 XC 9500 FB architecture lock has 5 product terms per macrocel 00 function bl ence, there are a «(18 x3) in the AND array. te Lae ower product terms ae associated with each macrocel withthe ea aloe, tisposibletous the vse pod ems fom Se withthe help ofaproducttrmallocatr.Konsss sone ches and gates to pass on oF accept the producttemstoor from te grannable si 1 aon wel ato cent te sum ems Rings died ct byes he product rms allocator ser the ipa pode msto peeof the functions. he product erm allocator i shown in Fig, 8.32 Product toms (re aten || pissin 4D To Mace ces) & J prodet term output con 44 aD 5, ) ouTeur » a U ‘Product tem cock i 1 product tera set PTR) = J =——| rode em OE Fig, 8.32 Product term allocator contains a flip-flop with some ‘The macrocell with the function block basically flip-flop. Ireanbe Hogrammable multiplexers to drive the inputs of the : inputs as well as selecting the combina®e Nefipsop can be programmed to behave as aT oD iP-0OP__ Programmable Logic Devices is uit in achip a8 aretangular stature, with column for 1s fas] — at Oy utpot ada pes transsor tech rosso Bate — pe ,010¥ con the given input and output to-contral aan aati wes pe omen ts tee peo sap PROGRAMMABLE GATEARRAY ___ on Ics ney Poh me devs wih i Cy Lc Ne at oneness ANG ete ANF FCA potas ypical PLD» put an FPGA chip contains much more logic than a CPLD of pas PCAl 7, PGA IC, the user can Prosar the functions realized by each logic rik. ok Fig. 833 XC 9500 macrocell Vo block of XC 9500 seen the cells. uch PGAs recalled as FPG, nner piso XC3500 family getroted trough an /Ooc teie meses Be a ee x Pi ch main An block s shown in Fig. 8.34, Fe en FPGA wobaseFPGA achicushnctene a ws rom Xilinx ond Acte| Bot the epenaches Inve Bes 38 patra es that ae Configurable and both of them have switching matrix to comet HEE cp | ies hese locks Sibercn th aoe] E Beery acccetyicallyhsconfgullopc hicks ns Oeas + "aero ching Te swing ihc bf sane merry chip. By set hs mena chip ws EPROM g satin gun datacan changed hese deve epg From Macmct!| PFOE_| ee (Slew A PGs, there aresimplebasiceels called as ogicmndesan} scones setae Thi architecture, due to the complex switching mt Re ble, Once itis configured, it cannot be changed. rutin, we will discuss the basic Xilinx FPGA architecture and neuen the popular FPGA series (XC 4000) architecture conttot ( Global OE se | LOE Sis] cnsoes {cxasoes Ti 834 XC 9500 VO Block 7.1 Xilinx FPGA Architecture ‘il. FPGA is basically made up of three modules: + Configurable logic block (CLB) + 110 block (IOB) * Switching matrix Figne 835 shows the general block diagram of FPGA structure ‘The WO block of XC 9500 provides three different analog controls. + Slew rate control For setting the rise and fall time of the output signals. + Pall-up register For preventing the output pins from floating at power-P {er programmable ground For providing ex ground pins to handle high dynamic currents at switching. WO block also obits movies aru conchae coutputcan be always awa contlled ty PTOE or global OF pins. ae provides compatiblity of devices operating at different supply ce Mae Xilinx FPGA architecturedata multiplexers, cont cco ee Aro route the data internally withthe configurable opie pe uptablee pon he FP sntplxersareus Figure 836shows 2000 series FPGA. ieurs Contin = /t— = sincton |] | severe clk Fig. 8.36 Xilinx XC 2000 CLB Combinational function generator Ikacceps four extemal inputs A, B,C, D, and the output of D can be extemal or feedback from the output selected by multiplexer M. The combinational function seneratr produces two ouputs,Fand G. With the help of multiplexers Ms and ‘Mc either combinational or registered outputs from F and G are available the uputs, and ¥. Alipelop Theconfigurabe logic block of XC 2000 contains aD flip-flop whose input Dis étiven by #outpt. ts SET, CLR, and CLK inputs can be driven by one ofthe iflerent sources as selected by multiplexers Ma, Ms, and My. Programmable multiplexers Taba :M; {0 My ar used to selet various options of input and output comection. They are programmed by writing the programmi inside he rege MOstarmed by writing the programming data in SRAM, Fier inan FPGA is required for providy L val back eno sae ditional controls on Os, like aCPLD-A Programmable > 10 pin aoa ].. clock ‘Ourput clock Fig. 8.37 Xilinx FPGA VO block ‘exis FPGA programmable HO block contains two flip-flops forregisteed tod egistered output, which ate connected to only one UO pin, since itis Fee tonal. The important controls which are provided in the UO black every 10pinare: ‘Output inversion control «Slew rate control «Tristate control + Actve/Passive pull-up control ‘Switching matrix structure nk. 8.38, mateix Structure of the switch switching matrix provides inconnection among CLBs and JOBS inside an OA. Every switch provides direct interconnection between adjacent CLBs or 108s. Inadition, a set of vertical and horizontal lines provides facility toconnest ‘W0CLBs within the FPGA. The general structure ofa switch matrix is shownoa 3.7.2 xC4 ont ae “itching matrix bl it a zi ass the Xilinx XC 4000 series FPG! ets yanding XC 40 vores aches es because the recent ce fn Xl se XCA00 ait ani 1000 Series FPGA . ectures of main modules within the phasic archi hin the FPG, aoe avebeen discussed. Inthis seen tion Thenced asi Ves asic ilding Ook The Xilinx 4000 series FP: nd many othe Feat sare similar to 2000 0F 3000 series but more np, wee added, Like a CPLD family the XC 4009 rman oho device size an input-output cepabltis, Table 8.12 mara pe device capacities ines of tei size of CL, wr of VOs, FFs, and the typical gate count foreach, family a0 ives an iden of amber of LBS, total Table a.12 Some Xilinx XC 4000 family devices [aoe pec tes] De ssi cae lemrpx | if | 360 | ask [remmee | sexs | 256 | tae | 708 | teak wee isc | ae | ae | 996 | Meise [reser ascas | aan | ae | 5376 | aoetamy frewsm) oxo | ane | 4 | ee | ss Letussce the main blocks of XC 4000 architecture, whic + Configurable logic block + WOblock Switching matrix Configurable logic block of XC 4000 Figure 839 showsasimplified block diagram ofan XC 4000 CLB. Itbasically has nine logic inputs (F,~ Fa, G\ ~ Gy, and H,) and three outputs F; G, and #. The combinational function generatorcan generate the outputs inthe following manner: + Two independent functions G and F of four variables, ie. Gli, Go» Go Gj) and FE, Fy Fy Fa. + One function H of thee variables, ve. H(F, G, 1) + Any function of five variables hy having F ~F,= Gy ~ Gy with Hy sree fn fee cig anne ables contains two D flip-flops withthe following features: + Enable Cock (EC) input + Direct St (SD) input + Direet Reset (RD) input The above inputs sources inate andi np likeDand CLK canbe seleted from multiple 'pof programmable multiplexers M;, M;, and Ms~Mg,asshow” in the block diagram, _—_Frogrammable Logie Devices iggy binational as well as registered output onthe wyes the com the outputs selected with the multiplexers ally 2 ee 8 fg VO. from on 20 Pe Cie Ge Gi Fig. 8.39 XC 4000 series CLB structure 10 Block of XC 4000 J 0 pin on the FPGA can be used for input or ourpat or both Hence ike {(DXC9500 family, XC 4000 series FPGA also contains an IOB having more lgcconol than CPLD. “gue 8:39 shows the I/O block of XC 4000 series FPGA. Every VO pin has ‘oD fip-lops associated with it. The input and output paths within the FPGA ‘cain hese D flip-flops selectable by multiplexers Ms and My Tel block's other logic controls are polarity selection of the four signals i el (OUT), three-state enable signal (7),an output clock (OCLK), ‘C40 clock (ICLK) enable with the help of multiplexers My Ma pg Ah UO block also has analog controls ike programmable sew rate of Wer and pull-up/pull-down resistor for /O pin. ictal nterconnects ‘mec connec programmable interconnect architecture provides very Gense and Li tivity ina small silicon area. These interconnections between blocks can be made in several ways, which are:carl [eee | 3 ty ga a t ° opts ea tap water Mi-My reuxen + Programmable Mux | reir Fig 840 VO block of XC 4000 restadaon msnrlaset of wires ih ropacinabie onmesioaa them. ymin Fig, 8.4L interconnect canbe grouped as lobal Ons, le ay eet ng ine The Cbal Coes opti os ee SSE es dot Norovide ort delay and minimal slew. The single ins are mae soc iat CL Scones, Double and lon linear optimized forshonet ay far longer comections. o SARE 6 4) 8, 4 Y Lime Date Sill : clock Fig. 841. Programmable interconnects ___Programmable Logie Devices = joa roeammate econ poet Peet ie ne aes ey doe wih aanced sate oh fm ie eects seared as long he dese pater he poh, Ets, Bef itis dove te solace pace enor Eto optimize the devie performance by finding a Setar ae el pets a he, Ng conten by 1c a allo asieaem Ss sppscTION SPECIFIC INTEGRATED CIRCUITS (ASICs) ei ene ote PA 3S Ow Pines gram table for a 3-bit Binary-to-Gr Ty the PLA program table fe ae dea tations of 8.22 1 8.24. converter having the output et Table 8.14. PLA program 1able for Example 8.6 Equations for ¥), Ya, Ys are: Ns PS+9s+POR cia he RS +5 + Pos+POR or 630) W=PQ+ P54 ORSig 8.52, Looping of mints fori, Ys and Ys ora PAL device, there is the equations re “Table 8.19 shows the PAL Pro Keamap for benefit of havin to be implemented as they ae ram table and Fig. 8.54 shows the PAL fuse 1gcommon produet terms. Hence, mp. rropepet P sf-Latel ems tpt tt i Sno Brine oie HH ga peat ras Bs mp 8.10. Design «priority encoder cireuit with 4 active high input fy 2—{z =) P, anays= 0) Mrand 3 active high outputs, A and B indicating the number of highest tis dvce requesting service and N. indicating no active requests. Input a Thohighest priority and f isthe lowest. Gi PF loglnentitusing a suitable PAL device, H+ pr ae Pe ‘etm sbe forthe priority encoder is given in Table 8.20. +t zi Table 8.20 Truth table for Example 8.10 _ a 2 > fe intact fuse blown Fig. 8.54 PAL fuse map diagram__Prosammate Losi Devices gpg PAL program table for Example 8.10 oreo ‘ i. 855. The K-maps ford and pare shown in Fi pee ‘Kemap to Fig. 855 Kmaps ford and 8 ree en jgir_ Derive PLA and PAL. programming tables fra combinational abit mum Azhii 37) str bit number. ih +l ny (83%) iit ea tint number having the Blas ad fae i weit bah ameaber (77=49 oF 110001) to be ¥st0 Yo raed fete abl forthe crit given in Table 822, {}— Py Table 8.22 Truth table for Example 8.11 : = | { Pr [ina Inputs Outputs i (All ass tact fe [Te Yrs [ee [is |e always =0) ipo yo jojo jo fe jo fe ~ Ht Jo Jofa jojo jo jo ial rs Meee [ooo jo: 1 4 Siege, | 1 ja) oe} o | jo rt TF + |i jojo jo |1 Jo jo Meo [1 jo |i io jo Peele |}: Jie bow} olor 5 i geen mia Ly | 1 |-1-L obo: i = B hesik ee Yoare givenin Fig. 8 56and ee “hee Tthtt opoTsyo| iff faa] 0 | Fig. 8.56 Programmed PAL for Example 8.10 nae ee theres need to use a PAL having 3 inputs, 3 outputs with minimum 2 Product terms (AND gates) per output OR gate. Table 8.21 shows the PAL Programming table for the 33 PAL and Fig. 8.56 shows its fuse map. K-map for Y Fig. 8.57 _K-maps Y5t0 Yorer are 8stinet prs xchat utptsitsct 302 ? table and Table’ 2 the PLA program therequited PL gta veceones su of pret exPres ryehrh n thle y= hit hle cos for Yst0 Yo areas follows: (839 640, Gay, 4 Gay (6.44) stohave its outputalways 0". Tableg.a38 sizeof y=0 Yes hls hh Be sans with all inputs intact. Fe pesien a sequence detector to detect the sequence 110, using Give state diagram and state table. Pat pts ous it zee ‘ sation the initial (reset) state, X as input and Z as output, Table 8.23 PLA program table for Example 8.17 Nee ra et ty sonitedag ut enacts Tapas Oa peat diagram i Product a som fe i fe fe ee ee ag) X-~--1OLTOION 110110. ‘)-|-1- ut Sad i | - |r 1001001000001... fered Pee = (41) of le pla) fu] ate ae oe a eee aay} \— |i) 1] eae @) Cw oe) the 6 ={9{o}-|-1-)1) am bhi , eas oo) A | a E Fig. 8.58 State diagram for ample 8.12 th meee |=) ee 3 ririri[riri(e Init above state diagram, state B indicates occurrence of one 1. State C ‘lees occurrence of two 1s. Hence, the circuit remains instate C till itreceives all Slate Dindicates that 110 is received, hence it returns to B with output = 1 if Table 8.24 PAL program table for Example 8.11 Inssvedis 1 else itretuns to inital condion with ouput = 0 ee oe stat table is given in Table 8.25. ee Table 8.25. State table for Example 8.12 Bs I 1 I - = Pr — 7 nf 2 - S Cy a Peale aaro | > = 2 hh i r 3 Y=bh +hh us eis) 3 aecna| £ c Bhi 6 if ‘ : Yq=[gh lot Fehto ee Contexe vonatseons_— the state assignment api, C=10, D=1l Let for Example 8.12 FF inputs | Oupay a a 0 fo 0 1 a 0 oie la yf omg ma ee oon) eae oe eat 210 Noo no = *\ 0 oF 9 ofiyefe] fofofo ifofutoki) [ie Knap ie, Kap for Dy Fig, 859 Kemaps fr Example 8.12 Dy =D,04+X0,05 (8.46) Dy=X0,04+KQs 00+ X 405 (a7 (Q105 (8.48) From the equations, there are 5 distinct product terms. Hence, we need a PLA. ith 3 inputs, 3 outputs and 5 product terms, Also, we need two D flip-flops connected atthe outputs of PLA, as given in Fig. 8.60. Table 8.27 PLA program table for Example 8.12 Programmable Loge Devices 5 213. Implement the state diagram shown in Fig, 8.61 using PAL, fhebesiz of PAL required. j mw Fig. 8.61 State diagram ‘ese able forthe state diagram of Fig. 8.61 is given in Table 8.28. Table 8.28 State table for Example 8.13e 1s, 4 outputs with minimum 2 produet io ae gine input fence the Dip-fops instead of using eee ae Fi OR Sere output PAL whose outputs canbe used mee ipopstoimptenentit Lets ave Dr Prad Dag econ sea ic so eeiada omens eile treet pgs wn ot yes fou alah ae Table 82. 8 posse AL roeram table and Fig. 8.63 shows the PAL logic ae js 9 sit unas bxcaton es ga eat proum ube for ample 13 ee Inputs: @ [| * Cees sen Sahn asc aiyey| p|ea ca eae Tlo | ° ofa fo alent Ble cule poet te Supe : _ | lL | L | z2x0 px 1 1 10 ooTe Toe] al of ol olf " eat sl tne Po 2, wtf o[ x 6: Tey . Kamp ieD, Se ae Keimap for De i Fig. 862 K-maps for Dy, Dp, Dc, Z | eerie paar Ea tei ager 649) D . Pr OLE + Fc cata Pe) ao i oa BSD et ‘ (652) iat + ee.rr aiion, we discussed some popular deyie, see nd ALIGN mex be contr ppl device 1188 rogrammable’ means that the function my re stern he ps tesa at smmable logic array (P PLA) ALA device basically contains an 2 si army of pro rae tn nb By ce bale i reer cont fale eta pt om me OR fain. ND ning ra ene PAL) PAL Evie ae ove PLDs Whe te ey Prgeaming ly sil toys mae: PALS consi of tay of i a OR se PLAS. The aor erence Dene PLA Seer PLA, but he aays ae programmable; wheres nd PAL devices is tht pe A_ OR aay sfx and AND array isprogrammeble Generic aray lpi evice (GAL) It contains a programmable AND array. a fixed ere da oat sate similar to aPAL dvi. The out stage i refered to ‘he ouput loge macrocell (OLMC) Sipelar PLD circuit The AND-OK arrays have bipolar elements Tike diode or ears present athe row-cokm junction in «PLA. Bair, PLA and PALL devices Tel te bipolar cieuts. Such bipolar PLDs are manufactured with all he diodes ree but wth tiny fusible ink in series with each. By applying special pats the device. one can select an individual link and by applying high voltage, these links ae fused, (CMOS PLD cireuit In ase of CMOS PLD circuits, instead of diode, an n-channel ‘casistor with programmable connection is placed at each intersection between an input and word line (row-column of aray). In CMOS PLDs, the programmable links tre generally no fused In non-felé programmable devices, the links connection is removed or established as part of the metal mask pattern generated by the ‘manufacturer, {CPLD) CPLD is a collection of individual ‘Complex programmable logic de erconnection structure that allows mb, ge cp wih proganmable th PLDs et coma as th wer wants hd erate ary Fs sir CPLDS ig ee eb snowing cmp il acon ke Chip A POA can iconic ingi ells wi prosamnae per sporammabe logic el less than peal PLD: tip contains much more logic than a CPLD of the same size. Programmable Logie Devices SS 2k —— saan t following! Jing programmable logic devices in between the GAL neta L om gered ont ation. yee rams for extant angel Sve re tems ten get TS: a roe CET gements of stangard /O. programmable 1/0, and ga eyo PAL: Ms texan rs fo en Mal eailecce termes 935M gomnsble Toc deview ec aasnm NC? ih rk pansion BOC mn neat agar, explain the features of XC 9500 CPLD thin the function block. ute eto 10 Bock in CPLD and eats provided in an VO block? ues tsie difference between a Xilinx | nats LB? What are the components of a simple Xitinx FPGA? “tats te technique used to implement a combinational funetion within as! ‘Eg he following modules of an XC 4000 FPGA device: (i Cinigarable logic block ()lat-Ourput block $0 Sich matrix 2 ee the types of ASICs? t ie Bet block diagrams, explain the difference between: Lee cellbased ASIC 4 Gute aay-based ASIC ple programmable logic device and a 500 CPLD, explain the roles of EPGA devices? What are the diferent ‘and an Actel FPGA architecture. it C.D) =ABD+ ABD CD) =A+BD °rogrammable Losic Devices _ $88 spat has been 1 for if and only if the in je ours iT able PAL device with standard /O saimgminsiesss wo wa. a.0 =D Be is seat flor’. uence et ames. Tie OP gos through the 564 junc) eS neh ores ee man es SrA sod ai gi ea 3 Bi sasita rk : KH TOA device wit eiseed outa oe able he etlowing factions ws 2. Realize the MP. O.RS) = EME. S, 67.8.1 10, 1,5.6,8.9, 11.13.14) following multiple out ombinatonal i 5, Design and implement the thing PAL and PLA devices (a Fllesobiractor or with less than, greater than, and equ (b) 2.0 compara {c) Excess to BCD code convert (a) 4b Grey-t0-Binary eode converter tonal cireuit for an 8-segment 64, 1thas 4 inputs, 2, ty output Design combinat Dany ater sieve nF, il He eaad Supa, 0 A 46 dam diay the doima equivalent of 4 ais recabarin rrcomplenent form For Yl example, the codes ae shown below: 00000 1000-7) ooid 1001-0 Me 864 oscem caro 101068) 011g) 11110 Segment should indicate the sig (ti it for ~1 (0 ~7 only) (a) Write the truth tale forthe circuit {() Show the maps and the equations suitable for implementation using PLA. (6) Implement these functions using PLA with minimum product terms. Draw the logie diagram, 5. Design a 4b synchronous binary counter using (@) D Bip ops (0) JK flip-ops Implement them using a suitable PLA, Draw the logic diagrams for (a) and (6) 6. Design and implement « BCD 4 BCD counter using a PAL with 16 inputs and 4 tiered expt. pei he numberof pret te een He aunbe of prod eit per oa (©) Draw the logic diagram.Chapter 9 | A/D ano D/A CONVERTERS ee ee Chapter Outline —_—-__7 Basic concepts of analogto-digtal conversion and vice versa, «Types of ADC and DAC «examples of ADC and DAC MEE genet cio 9.1, INTRODUCTION Real word processes produce analog signals that carry information, An analog Siena defined over a continuous period of time and its amplitude may assume a continuous rangeof values. Itisdfficulto store, compare, calculate, and manipulate this information with good accuracy using purely analog technology. Digital signal processing technology has a number of advantages over analog signa processing Therefore inmostof the applications, digital systems are prefered overanalog systems. But its found that most ofthe real data available isin analog, form, forexample, voice signal, output ofthe sensors, etc. Therefore itis necessary ‘oconvertanaog signalsint digital signals. An analog-to-digital converter(ADO) isused for thispurpose, After processing these digital data by a digital system, itis given oacontrol device or transmitted through an analog channel or measured by ananalog equipment. And hence, the output of adigital system should be converted intoan analog signal. A digital-to-analog converter (DAC) is used for this purpose. ‘he block diagram ofa digital system with analog input and output is shown in Fig. 91. Analog ‘amioe _| AD. | Digit DAL aa convener } system converter Fis. 9.1. Block diagram of digital sytem with analog input and output ‘This chapter discusses the most common A/D and D/A conversion techniques. yn involves translating digital inf yA) conver igital information slog (Pe formation. After processing the digital data by digital jog control device to drive the cursor ams ofa plotter Jhannel or measured by an analog equipment, nalO 7 oan anal analog cl ough an an atm should be converted No analog signal. The i peed OCONEE diagram of a S-bit DAC. Ithas thee input ines, Ds Mpatine which provides the analog signal. A bit agit 2a ons, rom000 0 111, The output analog voliagelevelis val cightcom“ombinations of Oand 1; tisminimum for 000 and maximum arate output analog signals in the range of Oo LV andthe Shia 900 to 111, Is equivalent analogs given in Table9.1 and go perween the digital signal input and the analog signal outputis shown ero af 99 ut and is 1 igi input eile anal | Anatog signal ov 1wy aay pa 38 V Ra pA as V pel 5i8Y os V Fig. 9.2. Block diagram of 78 abit DAC - 000 001 O10 OIF 100 tor 110 117 hack Digital input FIE9.3 The relation between digital input and analog outputist He nove table and Fig. 93 From the ab 1, The value of LSBis 5 ay 2, The vale of second LSB is — 21 Vy 3, The valve of Mb LSB is = 14, Pull scale output= Vp ~ Value of LSB phere nse numb of bis of digital signal and Vi the maximum amplitud, The put analog voltage Vai 2-4Vpp 22 ot Von 21) “4 Vines a the digital inputs of mbit DAC. Valo?” + where Voy Vou Von Example 9.1 Calculate the values ofthe LSB, MSB, and the full-scale output {or an 8bit DAC for 0 to 10 V analog output range. Solution Given data: n=8, Vq=10V Y,_10_ 10 Value of LS Value of LSB 961 V. 9.2.1 DAC Circuits The cites of digital-o-analog converters are of two types: (a) ResistordividerDAC (©) ROR ladder network DAC Resistor divider DAC his also known asa weighted resistor DAC. Each gl vel apt icone 22 into nequvalentanalog voltage or cure. Figure 9.4 shows the simplecireuit diagram of a 3:bit DAC. A 3-bit digital signal has ight combinations, from 000 to 111. The ouput analog voltage lve isa function of the inpa combinations of O and 1 andthe amplitude or reference voltages itis ‘minimum for 000 and maximum for 111 Fig. 9.4 3-bit DAC A/D and D/A Converters 6 coespondst00V jo cot pee 12 21 V: forthe np "7? = 2V, and for the input 100, the o 587, «e3-bit digital inputs reference voltages and V, re the 3 Pi nds toOV and logic I corresponds 010, uatput ser teagan ial Tet or spownnFigs9.5(@), 0) 00), Yo +7 Ry Ry =, o pana, ery Ay, © xd (€) 100 fess Dptal input applied tothe network (a) 001, () 010, an yume that the Joad resistance R, is greater than the output resi str, 4 fmfig 95(a, the output for the digital input 001, pye Po RRiMR + Ra), Ry + RiRy/(R, +R) VpRRy 1 RR, + RoR + RR, ___ Fam Fig.9.5(b), the output for the digital input 010, 2x, V : FOR, + RoR, + RyRy Fm Fig.95(0, the output forthe digital input 100, 4y2—__YoRRy RARER R, + RR, Eqs (9.1), (9.2), and (9.3), RD and Ry = Ry istance of the e) (9.2) 93)ek axa DAC and provide MOF AUTRE TEU Under yy circuit wll wrk a 2 shigherthan the output resistance ofthecincuie ovide accurate rest, To a¥oid this roblemy a re fad from the resistive network, The circuit ors The iris low, the cuit a pis used which so copramp is aes hl DAC with opamp is sown in Fis AIK A 5K, RK, R= 2K 946 bit DAC Analysis of circuit Assume the op-amp is ideal The voltage atthe inverting terminalis equal tothe stltge atte non-inverting terminal, The input current of op-amp is zero (J,= 0), the non-inverting terminalis prounded, Applying KCL to node I hthth=h+hs hahth=l — (sinceh=0) Chey 7K, 4) For the input 010, the output, A/D and D/A Converters 58) 5) (0.6) sy =4K,and Ry= 8K. These values are obisned from .tnen a= a Gye circuit is used to convert the digital data inputs (9.0). goat tis tne multiplying 4 emia by thesignal data. i iat nem gu |B Fear ig called a SBA py, ——} converter | Analog data eyes (bal iesenient ‘voltage waveform of a 3-bit resistor divider DAC for the jeed00, 001.111, is shown in Fig 9. OO O17 100 101110 —— Digital word —> "£98. Aralog output voltage waveform for a 3-bit resistor divider DAC 4 0007 a i Psbeetal finer the resolution of conversion and lessisthe step size cos andteie nan? a Stability of DAC are based on the accuracy of the Awan mere dependence, ies DAC requires a wide range of resistor values. As the length of ihe hess the range of resistor values needed also increases. Foran “ Targer values of resistor are 128 times the value ofthe Be weanDisa eons network DAC RAR ladies tO ir vider DAC isthe requirement of «Wide range ‘The major drawback of 81 ee DAC uses only tWOreSISOT Values, ales In conte : ofresitor val adder networks shown in FB. 99. Rand 28, The RI Y Fig. 99 The RR ladder network snip. 99, Yn Yad ovate 3g inputs voltage levelsand Wis the analog output Analysis ‘Trosasume the voltage comesponding ogi level 1s V9 Forthe digital input thine eet diagram of R2R ladder network is shown in Fig 910() and its guvtet cutis shown in Fig. 9.100). Pr the digital input signal 100, the ‘output analog volageis, Vax2R oe 97) 2R+2R om a Fey ites : 28 aa c As ak 328 aah 1 38 wh ¥, [oe Fig. 9.1006) Equivalent circuit of R/2R Fig. 9.1012). R/2R ladder network for the digital input 100 ladder network forthe digital input 10 For the digital input 010, the circuit diagram of R/2R ladder network is shown in Fig 9.11(a) and it equivalent circuit is shown in Fig, 9.11(). Fig. 9.11(6) Equivalent citcuit of R/2R ladder n for 010 Fig. 9.11) R/DR ladder network for 010 ode ue i100 i. 11 [ fs ‘A/D and D/A Converters 584. pisreplaced with ts Thevenin'sequivalent ‘it aR ky —o%s i oe c 3 cog 9126) wih Tavis equivalent valent . 30 ide nework of 908 8 te ga 010.the otra anal VRE asi po Mn (0.8) ie 8A ; 9 BRAK rut diagram of B/D der network shown linpat 001 fg. 9.126) WIR ladder network for 001 -Thevenin’s equivalent et edsidenetwork of node A isreplaced withits siustown in Fig. 9.12(0). 7 Fig.9.126) Equivalent of Fig, 9.12(a) with Thevenin’s equivalent flefthand side network of node A ‘eklvhand side network of node B is replaced with its Thevenin’s equivalent | Sithshown in Fig. 9.12(c), _ Equivalent of Fig, 9.13(6) with Thevenin’s equivalent ‘side network of node B eaead 1 oot, the outpat analog voltage is, y : 99) ne paes 0.10 ite anasitsobseried tat fr a8 DAC «reset + reveal NSB ricoup ming lng tr bADACIB ou 12) where Vp, Vos Vos we Y-ate the digital voltage levels. ‘The cirsitshown n Fig 9.10 works asa DAC, under the assumption that load resistance is high, It is low, the output of ladder network will be an incorrect ‘le, Therefore, ts needed to use the operational amplifier asa buffer to connect ‘he output of ladder network tothe load. The circuit of a 4-input DAC with an op- ampis shown in ig. 9.13. In Fig, 9.13 the op-amp is used in inverting mode. The amplifier acts as an inverting curenttothe voltage converter. The output voltage V,=—IR. Theanalysis ofthe cireutis same as above, Fi 9.13, inputs R/2R ladder network DAC with op-amp A/D and D/A Converts: _=s of a 4bit ladder, having the following ie voltage wre otro As 9 210 Wo yy 0110 wi feet 0 Siete it 1010 i yo we op etx 0x2? 112") 102+8) 625 as. 16: pst 110 ; ing siyox2 +12! + 1x2? + 022°) Me ms 2+) 16 Dg nga 1010 10{0x 2° +0%2! +0x2 +1x2"] aK ee Ye 7 _1o+8) a 6, Dial input 1111 10f0x2" +1x 2! +12? 412°] y= me nad tee 5.625 16 375 “pac Acshiioraresist complete 'tesistive divider network can be used as a DAC. The: & ofaDACiis shown in Fig. 9.14. : Digital ‘ u ee system Converter | ; FBS18 Complete block diagram of DAC94D ecto is loaded intoa Tlip-lop with logic 0, values of logic | and ete ome lip-flop stores Ibi data Digital are le. The output of Tipo 51 1 oF logic O may not be SAM Topeovidethe sme re used, The level extemal voltage source pe Sa when the input rom the ip-lop slow, the output 0 V. Tr pematic of a4-bit DAC is shown in Fig. 9.15. Ser 4 L rae + | ie i ee a Pee ene ‘ Fig. 9.15. Schematic of 4-bit DAC 9.2.3 Specifications of DAC The specifications of DAC which are generally specified by the designers are: © Accuracy i + Resolution Linearity «+ Setling time + Temperature sensitivity Accuracy Iisa measure of how See eetesiae the actual voltage is to the theoretical output value. aan rat dfines he maximum deviation ofthe tpt from the ide vod sey of DAC depends upon the accuracy ofthe precision resistor vonage ni vier r ladder network and the precision ofthe reference Specified as a percentage of full-scale or maximum output voltage. soltage forlogic Is and logic 0, the level amplifiers smi has tw inputs; ones the reference voltage from an ihe other nputisthe outputof the flip-flop. The amplifier Fa iat when the inpotfrom afip-fopishigh the output of theampliier. ete theoretical o ample, upPOSe oupat voltage i 10, example ty i 5 percent, it means that the pupa frat, scale digit vp inp is between 95 V 0 105 V oage of tas BEOEDAC forthe Wy specifies the maximum ero that can acai, seu pose the full-scale output voltage is 10 V ange HE and aximum error will be 10 mV (ue. 0.001 1 accuracy iss on et sates SBE cRNEINDS ADA edhe te reslton salva}sequl oe vege Shonen a estep sce. Its a function the number fis inte dia also esi gqrbt DAC using vies Vy" and ingle saa i invols i Pine aC sng alae tefl ele vokgs 6V eee ‘eNts te ut vokags cms inaseoti see = 3 usingthsconverter. heat ouptolageoubesy Sac re ta pode 9.6 he tl ceva woe DV. oe express the solution 8 pce The esas senltonis even by. stepsize Tull-scale @13) ‘The percentage resolution can be calculated as, Percentage resolution = 1 ak reeliiod eet es scents mae oun Foran mbitinput Percentage resolution er %100 015) “Togeta good resolution, the number ofinpotbits (2) of DACshoukshemasimin, Linearity maDAG, the relation between digital input and analog output shoul be Hine ‘Thats, an equal incrementin the numerical significance of the digital inputshould ‘eslt in equal increments in the analog output voltage. Ductothe eros insesisoe Vales, the input-output relationship isnt near. The inary enor ora _lnpuisthe difference between the expected voltae and he volage oie st the output of DAC. instant. change, the analog ouput doesnotchaneere referred to as the settling tim a Bee Temperature sensitivity ‘MeconpnesseinacitofDAC suchas renorreerence otge source davopanparesntve otonperatue- Due othe change in emperennen ge heseruasofanop amp evils olresorandeferencevolageman ge ‘ors he alo output volage for any xed digital input vaio ee tenga Tis changeinvaes with temeratureisknown anthem seu, is pete in eras of pp. 9.3 BASIC PRINCIPLE OF ADC An ADC does the inverse function of DAC. In DAC, the possible numberof ital inputs sxe. Forexample,ina4-bi DAC, there are 16 pone impo Butincaseofan ADC the inputanaog voltage canhaveany valve ina range a theta ouput can have only 2 discrete values for an N-bit ADC: The A rocessincludes sumpling of nput analog signal and then, each sample isemaverey noi binary equivalent. The block diagram of an ADC is shown in ag, Se lg free ee a ital erie aso = f Fis.9.17 Black diagram of ADC ‘Sample-and-hold circuit The sample-and-hotd day nl cept sample tr fied delay. The ed err Uevh se saplag easy hs per osesolnc coe frequency of 'Y should be greater than or equal to twice the band limited ' ofthe signal, The result of the samy (dn __alllh ea UV lop Fig. 9.18 Discrete signal aisorete signal is converted to binary with the help ofa conveter, The sc aignal, as shown in Fig. 9.18, is presen fora smal instant and hence the i Peannot convert it into binary. There isa need to hold the sample alone “funtion of conversion time. The sample-and-boldei elds it as shown in Fig 9.19, | Fig 9.19 Hold discrete signal ‘Asimple sample-and-hold circuitis shown in Fig. 9.20. Inthis circuit, the voltage across the capacitor follows the input signal voltage V; when the switch Sis closed. ‘Thecapacitor holds the instantaneous value ofthesignal voltage attained just before the ‘svitch is opened. Thus for every T,, the ‘switch is closed for a short duration and then opened. The de voltage across the ‘capacitor gives the value of the signal at the instant when the switch 'is opened, We can Saythatthe sample is captured aftera fixed (klay 7, This de voltage representsasample ofthe signal and is converted to digital ig ADC circuit during the holdina ens he Quantization and encoding Fre ADC the inputanalg vote canhaveany value inarange, anditis function aan te dial output can have only 2¥ discrete values for an N-bit ADC. sia ie whoterane of analog voltages required o be represented suitably Stora This processisknownas quamzation. Each intervals then assigned nique Wicbinary code, ich isrefered tas encoding Ta consider the analog voltage is in the range 0 to TV and a 3-bit digital snip. The whole ange of analog voltage is divided into eight intervals (2°) of Stepsiz = 1/8 Each interval isassigneda 3bit binary value. The interval ofthe analog volago andtheircoresponding digital values assigned are given in Table92. ‘These levels are known asthe quantization level. a Table 9.2_ Analog voltage and their corresponding digital values [-Aratog vottage Digital value | py 000 an 001 anv 010 sey att av 100 sey at oy TRY ia Daring the proceso comes mms of conversion te amplitude ofa discrete signal sat procera coat of qunizaton eve and then, itis encoded: The Fra eine e ampli ofa discrete signal to its nearest valve of on evel ieee quancation mantra tization intodues ero, This eor i referred oa the 'ximum quantization error for any analog voltage iS eta, A/D and D/A +l here Vis the maxiroum val i value of analog input “edb = 21 oc. The quantization eror wll be reduced ingens ey pots of ABC.) increasing the ses evel (ie 2") : w ‘a 3+bit ADC is shown in Fig. 9.22 faa eng seon analog AD. Tei inst ‘converter pert Fig. 9.22 Block diagram of 3-bit ADC have been developed to convert an analog signal inti en digital signal ‘Commonly used ADCs are: a ali compsor ADC ) counter tyPe ADC © Continsous type ADC 0 exsveaprosimaton ADC {e) Dualslope ADC 4,32 Parallel Comparator ADC (Flash Converter) ‘pens parle! comparator ADC uses 2" 1 comparators. Each compsrator Tere unkown analognput voltage withitsrefeence vole androvies cof pnte ouput. The comparison is peformed simultaneoisl, hence ts pnts ash ype ADC. Figure9.23showsa3-bit pall comparator ADC th ecieuit diagram, the op-amp is used in open loop. The open loop op-amp sesasacomparator,itcompares the input voltage with hereference voltage (fixed Yolage) and the output of op-amp is +Va Ot Vax- We can say thatthe output of {omparatoris high orlow (logic 1 orlogic 0). Thereferencevollagesare generated ‘Knpasimpleresistive network anda voltage source Vgand giventotheinvering ‘eminal of op-amp. The analog input signal is connected to the now-inverting teminal of op-amp. When the analog input voltage is greater than the reference ‘olage the output of comparator is high and when the analog input voltages ess ttanthe reference voltage, then the outpt of comparatoris low. The output ofthe ‘vomparator (1 or 0)is| loaded into the latch and decoded by the decoder, and we Bet ‘he digital output at D>, D,, and Do- Forexample Vsthe full-scale voltage, rom whichtherefeencevolag®V#'8; Wy, 3V 4/8, AV9/8, SV, OV9A8, 7Va/8 are generated using & simple este ‘etwork. The input analog voltage Vqiscompared simultaneously withthe referee Yolages by using comparators, The outputs ‘fcomparatrsarehigh orlow, which isa finetion ofthe input analog voltage. A 7-bitoutptisobsined from the fomparators, which is stored in latches. Tredecoder cicutconvetstis7-t sat into a 3-bit output. hi ‘comparator output andthe digital outputofa-itpraeleompual ‘in Table 9.3. Assume V_= 1 V. pifeent modsA/D and D/A Converters gg a 5 Aepaies 1908 1g ttc whit ee ag cca greece Paitage canbe oblained bya Sequence or binary cour OVP of decoder tie block ier of a4-bitcounter type ADCis shown in Fig 9.24 ps |»; [o, } Si oo ofo 1 1 ijt cone 2 | Digial 0 1 olo 1 t}o 1 1 t}o 1 1 L slog inpot Fig. 9.24 Counter type ADC “pels igram consists of DAC, acompardor, AND ge ania aaa DAC conver the digital dant analog sia ‘which is given as ent the comparator. Te opamp i used in open op 1a 8 ast tforend compares the analog int, which ha oe converted 0 ia) alg oupat of DAC. The AND gate provies the coe: tote binary Distal ver whenever the ousput of comparator is high, InoepgeeY ee rete reset signal goes low, the binary counter wllbesetto andthe output ie abatisvero(V,=0). When the reset signal goes high the clock pls is given arpetinry counter through the AND gate; its counted by the inary coun ia ‘TheDAC converts the digital output to an analog voltage and connects it to the Tutt comparator. The output of comparator enables the AND gale ops he a bck, The output of DAC increases with time and the analog ‘output voltage waveform is arising staircase, as shown in Fig. 9.25. ommnaee mecoome Fig. 9.23 5it parallel comparator ADC ‘Theprincipl of parallel comparator ADCis he simplestin concept and its typical convertion tne 0005, ; Bat eaue nresestetcandaett MENTof compartir whiehacing. MoE prime ale a a fas the pe analog input VORB om eran analog inp S mets conser an analog i ADC type conversion sequence Jog int on , 9.26 Continuous type ADC Description Fi Table 9.4 Counter aoa] oemer] | sina susiagam consists of& DAC, a compart nu own ci an ey] 1316 | > ¥-|Enble the AND gate to pase the cece tock dia SAC converts the digital data into ansiog signal, whichis tear | ans | te | 1, mae he AND eae pus he en at 2 Tg terminal ofthe Comparator, andthe no-nveing inp heel 1316 | vy>¥ [Enable the AND gate to pass the cic, great iY onnected tothe unknown analog input voltage V,, The opamp ¥,>V male the AND pate to past he cnet. Secumperngo, acts asa comparator an compares theaalog input as spun oP jimto digital with the analog output of DAC, The conto cet a6 1a | oo 1 3] ptoo | ate | 13716 | va>¥ Enable the AND gate to pass the clk oe i 1 rarer cle es te iiss AND esc pee dea ec oton of upldown counter based onthe rest of eomparatr Pa eRe eye lealtas dw once ae cn Oe ut of comparator in gh ste. Then ea [fs |u| ae |e femme aca pw ee set ibn AC uptime Tehri a one [5 | tno | sie fa > mt AND Ee os te sk ceive aan a | 10 | 1001 [one | ne [> amie be AND po ec ae ane V, the outpat of eoraparator i in Tow state. The counters then || oto fel asus | 27m be AND ate pth Se ma HOWN and the DAC output decreases, The ne it da 12 | 1011 ]11716] 13/6 | v4>V¥, [Enable the AND gate to pass the clock ‘verted and compared with an unknown analog voltage, This process of counting: TV, i greater han Vy, Figue 927 shows the anal inp dwn continues, until signal and the input to up-down counter. | 13 } 1100 |izm6] 1316 | va>¥,[Emble the AND gate to pas the clack inot [136] 13716 | ¥ic¥, [Disable the AND gate o pa te cok ‘Tracking enor Inths ADC thecounteradvances by one count for every lock pulse, therefore the clock sped decides the conversion peed, The conversion time is variable and Analg signal itis proportional tothe amplitude ofthe analog input voltage. The average | (arte) conversion ime ofan n-bit ADC i, wi Doug ia ca 4 aryl a 0.16) UpiDown input fs tpcoumter het fi othe frequency of clock oele. p=1,0n=0) In this conve a sion process, the counter is reset for each discrete sample. 3 wy Fig 9.27 The analog input signal and the input to UP/DOWN counter ‘Therefore ittakes along conversion time 9.34 Continuous Type ADC 93.5 Successive-approximation ADC The long conver Misahigh-resoluti somparator witha variablereferenct fom he rea etter ype ADC can be eiminaed by counting ‘elage Tye ution ADC thatuses only one ong by asequnceo Bn onetsion The ae wn lt, instead of resetting the counter foreach aDAC, eee ofthis ADC is that the unknown 208 Fig. 926 “gram @ 4-bit of continuous type ADC is shown in é » The ae gl ale by tryingone bitattime, ¥ ‘with the MSB. The block diagram of a4-bitst ‘ ‘is shown in Fig, 9.28.

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